Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-04-05
2001-12-11
Cuneo, K. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C361S768000, C361S777000, C228S254000, C257S779000, C257S738000, C257S778000
Reexamination Certificate
active
06329608
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of microelectronic devices and more particularly to solder bumps for microelectronic devices.
BACKGROUND OF THE INVENTION
High performance microelectronic devices often use solder balls or solder bumps for electrical and mechanical interconnection to other microelectronic devices. For example, a very large scale integration (VLSI) chip may be electrically connected to a circuit board or other next level packaging substrate using solder balls or solder bumps. This connection technology is also referred to as “Controlled Collapse Chip Connection—C4” or “flip-chip” technology, and will be referred to herein as “solder bumps”.
A significant advance in this technology is disclosed in U.S. Pat. No. 5,162,257 to Yung entitled “Solder Bump Fabrication Method” and assigned to the assignee of the present invention. In this patent, an under bump metallurgy is formed on the microelectronic substrate including contact pads, and solder bumps are formed on the under bump metallurgy opposite the contact pads. The under bump metallurgy between the solder bumps and the contact pads is converted to an intermetallic which is resistant to etchants used to etch the under bump metallurgy between solder bumps. Accordingly, the base of the solder bumps is preserved.
In many circumstances, it may be desired to provide a solder bump on the substrate at a location remote from the contact pad and also form an electrical connection between the contact pad and the solder bump. For example, a microelectronic substrate may be initially designed for wire bonding with the contact pads arranged around the outer edge of the substrate. At a later time it may be desired to use the microelectronic substrate in an application requiring solder bumps to be placed in the interior of the substrate. In order to achieve the placement of a solder bump on the interior of the substrate away from the respective contact pad, an interconnection or redistribution routing conductor may be necessary.
U.S. Pat. No. 5,327,013 to Moore et al. entitled “Solder Bumping of Integrated Circuit Die” discloses a method for forming a redistribution routing conductor and solder bump on an integrated circuit die. This method includes forming a terminal of an electrically conductive, solder-wettable composite material. The terminal includes a bond pad overlying the passivation layer remote from a metal contact and a runner that extends from the pad to the metal contact. A body of solder is reflowed onto the bond pad to form a bump bonded to the pad and electrically coupled through the runner.
In this method, however, the solder bump is formed by pressing a microsphere of a solder alloy onto the bond pad. In addition, the spread of solder along the runner during reflow is limited. In the illustrated embodiment, a solder stop formed of a polymeric solder resist material is applied to the runner to confine the solder to the bond pad.
Notwithstanding the above mentioned references, there continues to exist a need in the art for methods of producing redistribution routing conductors and solder bumps efficiently and at a reduced cost.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved method of forming a redistribution routing conductor.
It is another object of the present invention to provide a method of forming a redistribution routing conductor which can be integrally formed together with an associated solder bump.
These and other objects are provided, according to the present invention, by forming an under bump metallurgy layer on the microelectronic substrate and forming a solder structure including an elongate portion and an enlarged width portion on the under bump metallurgy layer. The solder structure can be formed by electroplating on the desired portions of the under bump metallurgy layer which are defined by a mask. The excess portions of under bump metallurgy not covered by solder can then be selectively removed using the solder structure as a mask. Accordingly, a single masking step can be used to define both the solder structure and the under bump metallurgy layer.
The solder can then be made to flow. Unexpectedly, the surface tension within the solder will cause the flowing solder to form a thin solder layer on the elongate portion of the under bump metallurgy layer and a raised solder bump on the enlarged width portion of the under bump metallurgy layer. Accordingly, a single solder deposition step followed by a solder flow step (typically induced by heat) can be used to form a solder structure including both a thin elongate portion and a raised enlarged width portion.
In one embodiment, the present invention includes a method of forming a redistribution routing conductor on a microelectronic substrate including an electrical contact pad at a surface of the microelectronic substrate. This method includes the steps of forming an under bump metallurgy layer on the surface, and forming a solder structure on the under bump metallurgy layer opposite the microelectronic substrate. The under bump metallurgy layer electrically contacts the electrical contact pad, and the solder structure includes an elongate portion and an enlarged width portion.
The step of forming a solder structure preferably includes the step of forming a solder structure including an elongate portion which extends over the electrical contact pad. This solder structure may define first (exposed) and second (unexposed) portions of the under bump metallurgy layer, and the step of forming a solder structure may be followed by the step of selectively removing the first (exposed) portion of the under bump metallurgy layer which is not covered by the solder structure. Accordingly, the solder structure can be used as a masking layer to selectively remove the first portion of the under bump metallurgy layer not covered by solder after forming the solder structure, thereby eliminating the need for separate photolithography steps to pattern the solder structure and the under bump metallurgy layer.
The elongate solder portion preferably has one end that is positioned on the under bump metallurgy layer opposite the contact pad and a second end that is connected to the enlarged width portion. Accordingly, the solder structure defines respective elongate and enlarged width portions of the under bump metallurgy layers, and one end of the elongate portion of the under bump metallurgy layer preferably makes electrical contact with the contact pad. It will be understood that other elongate solder portions may extend across the under bump metallurgy layer in other directions from the point opposite the contact pad, and also that the elongate portion may extend slightly beyond the point opposite the contact pad.
This method may also include the step of causing the solder in the solder structure to flow from the elongate portion to the enlarged width portion. Accordingly, a raised solder bump may be formed in the enlarged width portion of the solder structure and a thin solder layer may be formed in the elongate portion of the solder structure. This step is preferably accomplished by heating the solder above its liquidus temperature and confining it to the elongate and enlarged width portions of the under bump metallurgy layer so that surface tension induced internal pressures cause the solder to flow to the enlarged width portions. The flowing solder may be confined by forming a solder dam layer on the first (exposed) portion of the under bump metallurgy layer which is not covered by the solder structure.
The step of causing the solder structure to flow may form an intermetallic region between the under bump metallurgy layer and the solder structure. This intermetallic region includes a constituent of the metallurgy layer and a constituent of the solder structure. This intermetallic region is resistant to etchants used to remove the first (exposed) portion of the under bump metallurgy layer thereby reducing undercutting of the solder structure.
The step of forming the under bump metallu
Mis Joseph Daniel
Rinne Glenn A.
Cuneo K.
Myers Bigel & Sibley & Sajovec
Unitive International Limited
LandOfFree
Key-shaped solder bumps and under bump metallurgy does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Key-shaped solder bumps and under bump metallurgy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Key-shaped solder bumps and under bump metallurgy will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567206