Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-22
2003-11-11
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S690000, C257S773000, C257S774000
Reexamination Certificate
active
06645857
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to forming non electrically shorting voids such as vias and contacts in a fill material between two structures.
BACKGROUND
Monolithic integrated circuits are typically formed in a series of steps where a first layer is formed and patterned, and then an overlying layer is formed and patterned. With variations on this basic process, many such layers are typically formed and patterned until the integrated circuit is completed. As device geometries have shrunk, however, or in other words as the various structures within an integrated circuit are made increasingly smaller and placed increasingly closer one to another, new problems have arisen in regard to the basic process of integrated circuit fabrication.
For example, if the space between structures decreases, and the structures tend to remain at a relatively constant height, then the aspect ratio of the space between the structures tends to increase, or in other words, the measure of the height of the space between the structures as divided by the measure of the width of the space between the structures tends to increase.
While an increasing aspect ratio of a space between adjacent structures on an integrated circuit does not appear to be a dramatic problem in and of itself, it actually introduces several issues which should be analyzed and overcome in order to create a reliable integrated circuit that functions in the intended manner. For example, when a space has a relatively high aspect ratio, it tends to be more difficult to fill in with the layer that is subsequently formed. Specifically, the material of the subsequently formed layer tends to build up around the top edges of the adjacent structures that define the space, and inhibits additional material from entering the space. This tends to result in a void left in the space, which is not filled with the newly deposited material. Such voids are commonly called key holes.
When a key hole is formed, it tends to run the length of the space between the two adjacent structures. If structures such as vias or contacts are subsequently formed in the material deposited between the structures, the key holes may present a problem. For example, if two via holes are etched through the material, the key hole may provide an open conduit between the two via holes. When the conductive via material for the vias is subsequently deposited in the via holes, some of the conductive material may be deposited into the key hole from each of the two via holes, which can lead to an electrical short being formed through the key hole between the two vias.
Another problem with such key holes is that they can introduce a source of contamination to the structures of the integrated circuit. For example, in the case of the formation of vias, as described briefly above, the key hole between two via holes may trap some of the materials and chemicals used to form the via holes. Because the key hole tends to be rather small and is not directly accessible, it tends to be relatively difficult to clean out during normal processing. Therefore, the contaminants that collect in the key hole during standard processing may not be removed, as they preferably should be.
At a later point in the processing of the integrated circuit, such as when electrically conductive vias or other structures are formed, the contaminants in the key hole may inhibit proper formation of the vias. In addition, such contaminants may work over time to inhibit proper operation of the via, resulting in a failure at a later point in time and reducing the reliability of the integrated circuits so fabricated. Such problems can exist even when the key hole does not bridge a gap between adjacent vias.
One method to overcome the problem with key holes is to use new fill materials that deposit in a more uniform fashion, and which are less susceptible to the formation of key holes. However, as device geometries continue to shrink, the materials that first worked with a given aspect ratio may not continue to work as the aspect ratio continues to increase, and thus even more new materials must be identified and new processes created. Further compounding this issue is that as device geometries shrink, the fill material that is used between adjacent structures, such as an electrically insulating fill material, must have certain properties, such as high structural integrity or a low dielectric constant. Some of the these desired properties may not be compatible with the likewise desired property of not forming key holes.
What is needed, therefore, is a method by which materials that tend to form key holes can be reliably used as the fill material between adjacent structures, while overcoming the problems of contamination and electrical shorting.
SUMMARY
The above and other needs are met by a method of forming an electrically conductive via that abuts a key hole formed in filler material. A void is etched through the filler material in which the key hole is formed, thereby forming a link between the void and the key hole. A liner is formed within the void, where the liner is formed to a thickness that is at least about half a minimum cross sectional dimension of the key hole, so as to plug the link between the void and the key hole and thereby trap any contaminants within the key hole. Electrically conductive via material is deposited within the void to form the via.
In this manner, the liner material prohibits and preferably prevents contaminants that are trapped within the key hole from contacting the electrically conductive via material, and damaging it. Thus, a more reliable via is formed according to a method of the present invention.
According to another aspect of the invention, there is described a method of forming a first electrically conductive via adjacent a second electrically conductive via, where the first electrically conductive via and the second electrically conductive via each abut a common key hole formed in a non electrically conductive filler material. A first void and a second void are etched through the non electrically conductive filler material in which the key hole is formed, thereby forming a first link between the first void and the key hole and a second link between the second void and the key hole. An electrically conductive liner is formed within the first void and the second void, where the liner is formed to a thickness that is at least about half a minimum cross sectional dimension of the key hole, so as to plug the first link between the first void and the key hole and the second link between the second void and the key hole, and thereby trap any contaminants within the key hole. The liner is formed in a manner such that liner material entering the key hole from the first void does not contact liner material entering the key hole from the second void. Electrically conductive via material is deposited within the first void and the second void to respectively form the first via and the second via.
This embodiment has the benefits of the first embodiment, but has an additional benefit of not having an electric short between the two vias, because the liner is formed in a manner such that liner material entering the key hole from the first void does not contact liner material entering the key hole from the second void. Thus, the liner material may be electrically conductive.
According to yet another aspect of the invention, there is described a method of forming a first electrically conductive via adjacent a second electrically conductive via, where the first electrically conductive via and the second electrically conductive via each abut a common key hole formed in a filler material. A first void and a second void are etched through the filler material in which the key hole is formed, thereby forming a first link between the first void and the key hole and a second link between the second void and the key hole. A non electrically conductive liner is formed within the first void and the second void. The liner is
Ramachandran Ashwin
Whitefield Bruce J.
Everhart Caridad
LSI Logic Corporation
Luedeka Neely & Graham
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