Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-08-16
2002-07-30
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C324S765010, C438S018000
Reexamination Certificate
active
06426516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to testing conductive patterns in integrated circuits and more particularly to an improved system for identifying the location of defects in conductive patterns.
2. Description of the Related Art
State of the art integrated circuits, such as semiconductor chips, include multiple levels of patterned wiring (e.g., levels M
1
-M
4
). During manufacturing, the patterned conductors are tested for defects. In one form of testing, contact chains (which connect thousands of contacts/conductors on a give area of a chip) are formed and tested for electrical conductivity. One such contact chain is referred to as a “kerf” contact chain. The kerf is the area which will be removed during the separation of chips on a wafer. The chains are formed by contacts in these “kerf” areas and the chains are broken when the chips are separated and the kerf region is removed.
FIGS. 1A and 1B
illustrate conventional serpentine contact chains. More specifically,
FIGS. 1A and 1B
illustrate one metalization level (e.g., M
1
) of a semiconductor integrated circuit. As shown most clearly in the enlarged view in
FIG. 1B
, contacts
10
connect each of the rows of metal wiring with succeeding and preceding rows such that, as shown most clearly in
FIG. 1A
, all the wiring forms one large conductive circuit (only a portion of which is shown in FIG.
1
A).
FIG. 1C
illustrates a cross-section of a polysilicon level
102
within an integrated circuit chip, a first metalization level
100
, a second metalization level
101
and conductive studs
103
connecting the different levels.
If any one element in a contact chain is defective, the entire chain will fail electrical testing. However, there is no conventional mechanism for isolating which contact/row in the contact chain failed without a destructive test.
For years the failure analysis community has been unable to provide timely and accurate assessments of quality and reliability in contact chains. Trying to isolate a problem and determine if that problem is with one contact, many random contacts, or all contacts is extremely time consuming and impractical. Time wasted in analysis increases costs and decreases yield. Thus, faster turnaround time is greatly needed.
There is also a problem of accuracy in the conventional destructive analysis. More specifically, the conventional systems make contact to a very thin line
10
in order to take a measurement. Such contact often damages the line
10
. The resulting damage adds error to any measurement, and therefore affects the analysis adversely. Therefore, there is a need for an improved system and method which can quickly determine which contact in a chain is defective without damaging any contact in the chain.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit technology segment test structure that includes a plurality of technology test structures connected together as a chain of elements and a plurality of externally probable regions positioned along the chain of elements. The externally probable regions are positioned so as to enable location of a failed test structure. The externally probable regions include probe pads connected to the chain of elements. The chain of elements includes a plurality of rows and contacts connecting each row to an adjacent row, such that the contacts form a serpentine chain with the rows. The externally probable regions are connected to and are larger than the contacts, and they permit individual testing of each of the rows. The technology test structures are a wiring level in an integrated circuit.
Another embodiment of the invention is an integrated circuit chip that includes a plurality of devices connected together as a test chain and a plurality of probe pads positioned along the test chain. The probe pads are positioned so as to locate of a defective device in the test chain. The test chain includes a plurality of rows of the devices and the contacts connect each row to an adjacent row, such that the contacts form a serpentine test chain with the rows. The probe pads are connected to and are larger than the contacts, and they permit individual testing of each of the rows. The devices are a wiring level in an integrated circuit.
Yet another embodiment of the invention is a wafer having plurality of integrated circuit chips, each of the chips includes a plurality of devices connected together as a test chain, and a plurality of probe pads positioned along the test chain. The probe pads are positioned so as to locate of a defective device in the test chain. The test chain comprises a plurality of rows of the devices. The contacts connect each row to an adjacent row, such that the contacts form a serpentine test chain with the rows. The probe pads are connected to and are larger than the contacts, and they permit individual testing of each of the rows. The devices are a wiring level in an integrated circuit. The probe pads are positioned between the integrated circuit chips, such that the probe pads are removed when the integrated circuit chips are separated.
Therefore, with the invention, the location of the defect in a defective chain can be precisely determined without damaging any element of the chain.
REFERENCES:
patent: 4918377 (1990-04-01), Buehler et al.
patent: 5051690 (1991-09-01), Maly et al.
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5637186 (1997-06-01), Liu et al.
patent: 5831446 (1998-11-01), So et al.
patent: 5923047 (1999-07-01), Chia et al.
patent: 06-088852 (1994-03-01), None
Shultis, D.E., “Semiconductor Wafer Testing”, Dec. 1970, IBM Technical Disclosure Bulletin, vol. 13, No. 7, p. 1793.
International Business Machines - Corporation
McGinn & Gibb PLLC
Walter, Jr. Esq. Howard J.
Weiss Howard
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