Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-09
2011-08-09
Bradley, Matthew (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C365S049100
Reexamination Certificate
active
07996619
ABSTRACT:
A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way within a plurality based on a first portion of the address. The control logic may match the first portion of the address to a predefined value in a mapping table, wherein the predefined value in the mapping table is associated with the way. In addition, the control logic may map the address to a set within cache based on a second portion of the address.
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Bradley Matthew
Intel Corporation
Trop Pruner & Hu P.C.
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