Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-03-01
2003-12-09
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S118000, C714S733000, C714S736000
Reexamination Certificate
active
06662133
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to repairing integrated circuits and in particular to a method and apparatus for cumulatively repairing arrays in an integrated circuit.
2. Description of Related Art
Traditional interconnect testing, like that described in Joint Test Action Group (JTAG) Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1, has a strong dependence on software interaction and scan functions. IBM has expanded this single card testing concept in the original JTAG specification to multiple card testing within a system (Wire Test). The traditional Wire Test method involves scanning test patterns into the boundary latches of all chips in a system interface, sampling at all chips' interfaces, and scanning the patterns out of each chip to compare the resulting patterns. This process is repeated so that every driver drives at least once in the system, with multiple patterns on each interface, to determine and diagnose problems such as shorts and opens on these interfaces, if they exist. In this manner, it can be determined if all interconnections between chips in a system are intact. Manufacturing and system assembly relies heavily on such patterns to test systems as they are built and to diagnose manufacturing problems.
In general, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to an expected output. One well known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This circuit also is called an array built-in self-test (ABIST) circuit or engine. This type of technology allows for high speed testing without having to force correspondence between the array and input/output connections to the chip itself. Random access memory on a chip, such as the memory provided for processors, are usually tested using an ABIST engine.
It is increasingly common to have multiple arrays present on a chip. In testing these arrays, some arrays only need a subset of some tests that are performed on the set of arrays. Other tests may not work on all of the arrays, thereby requiring special test circuitry in certain circumstances. A microprocessor's ABIST may report failing array addresses for some arrays for each ABIST run. However, arrays may fail in multiple ways at different voltage points or frequencies.
Presently, a trend exists towards smaller electronic components which has resulted in higher component density and greater circuit complexity on a given-sized circuit board. The increase in circuit complexity has increased the difficulty of accomplishing in-circuit testing by physically accessing the circuits with a test fixture so that the response of the circuits to an external stimulus can be sensed. Indeed, as surface-mounted components (i.e., components which are mounted on a major surface of the circuit board) proliferate, physical access to the circuits on the board by traditional test fixtures may become impossible. For these reasons, much effort has been devoted to developing alternative testing techniques.
A testing technique known as “boundary scan” has gained prominence as an alternative to traditional in-circuit testing by physically accessing the board through a test fixture. The boundary scan testing technique is embodied in a detailed specification (Version 2.0) authored by an international standards committee known as the Joint Test Action Group (JTAG).
Accomplishing boundary scan testing requires that in addition to its normal application logic, each active component (e.g., integrated circuits) be fabricated with circuits known as “boundary scan cells” (BSCs) whose details are described in the JTAG standard. Each BSC is coupled between the application logic and one of the functional input and output pins of the integrated circuit such that each functional input and output pin is coupled to a separate one of a normal data input and normal data output, respectively, of the BSC.
During normal operation of the integrated circuit, the signal applied to each functional input pin passes through the corresponding BSC and then into the application logic without effect. Similarly, signals from the application logic pass through the corresponding BSCs to each separate functional output pin without effect. Thus, the normal operation of the integrated circuit remains unaffected by the BSCs.
In addition to its normal data input and output, each BSC has a test data input and test data output (also known as test access ports) connected so that each bit of a test vector applied to the test data input is serially shifted to the test data output of the BSC during operation thereof in a test mode. Also, the test data input of each BSC is linked to its normal data output so the test vector bit, shifted into the BSC during testing, can be applied to its normal data output.
Since integrated circuit arrays may fail differently at different voltages and/or frequencies, it would be advantageous to have an improved method and apparatus for using JTAG to control ABIST and perform cumulative array correction over different voltages and frequencies.
SUMMARY OF THE INVENTION
A method is provided for repairing a plurality of arrays on a processor with an on chip built in self test engine on the processor. A subset of the plurality of arrays is selected for testing. Data patterns are sent from the on chip built in self test engine to the subset of the plurality of arrays on the processor at a plurality of operating parameters. A response is received at the on chip built in self test engine from the subset of the plurality of arrays at the plurality of operating parameters. The response from the subset of the plurality of arrays is compared to an expected response using the on chip built in self test engine, wherein the on chip built in self test engine compares the response from the subset of the plurality of arrays with a plurality of JTAG based instructions.
REFERENCES:
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patent: 6115763 (2000-09-01), Douskey et al.
patent: 6259637 (2001-07-01), Wood et al.
patent: 6374370 (2002-04-01), Bockhaus et al.
patent: 6393594 (2002-05-01), Anderson et al.
Engel Christopher John
James Norman Karl
Monwai Brian Chan
Reick Kevin F.
Shephard, III Philip George
International Business Machines - Corporation
McBurney Mark E.
Wachsman Hal
Yee Duke W.
Yociss Lisa L. B.
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