Josephson memory and read/write circuit

Details Josephson memory and read/write circuit Josephson memory and read/write circuit

1989-10-23

1990-11-27

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Superconductive

307306, 307269, G11C 1144, H03K 338, H03K 513, H03L 700

Patent

active

049742051

ABSTRACT:
A Josephson memory circuit driven by first, second and third clock signals includes a write circuit which holds data as a circulating current circulating in a superconducting closed loop including a Josephson junction. The data to be held is supplied thereto through a data line with timing of the third clock signal. A first OR circuit is supplied with a bias from a read bias line with timing of the second clock signal and supplied with the circulating current. The first OR circuit has a Josephson junction which is switched to a finite resistance state by the circulating current. A second OR circuit is supplied as a bias with output data form the first OR circuit with timing of the second clock signal and supplied with a read address signal from a read address line with timing of the first clock signal. The second OR circuit has a Josephson junction which is switched to a finite resistance state by the read address signal. A third OR circuit is supplied with a bias from a read line with timing of the second clock signal and supplied with output data from the second OR circuit. The third OR circuit has a Josephsoh junction which is switched to a finite resistance state by the output data supplied from the second OR circuit. The data held in the write circuit is read out therefrom and transferred to the read line through the first, second and third OR circuits in this order.

REFERENCES:
S. M. Faris et al., "Basic Design of a Josephson Technology Cache Memory", IBM J. Res. Develop, vol. 24, No. 2, Mar. 1980.
W. H. Henkels, "Josephson Feedback Memory Cells", IBM Technical Disclosure Bulletin, vol. 18, No. 11, Apr. 1976.
W. H. Henkels, "Low-Current-Level Widest-Margin Josephson NDRO Cell", IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun. 1978.

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