Jitter tolerant delay-locked loop circuit

Details Jitter tolerant delay-locked loop circuit Jitter tolerant delay-locked loop circuit

2005-12-13

2009-11-17

Connolly, Mark (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000

Reexamination Certificate

active

07620839

ABSTRACT:
Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

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International Search Report and Written Opinion of the ISA, mailed to applicant Apr. 7, 2008.
U.S. Appl. No. 10/701,005, Johnson et al.

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