Jitter reduction system in digital demultiplexers

Details Jitter reduction system in digital demultiplexers Jitter reduction system in digital demultiplexers

1995-03-28

1997-01-28

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370506, H04L 700, H04L 2536, H04L 2540

Patent

active

055984452

ABSTRACT:
An elastic read-write memory subassembly (EM, WP, WA, RP, RA), whose read clock (RCK) varies its frequency with a signal provided by a phase detector (PHC) as a function of the difference in time at which two pointers, for read (RP) and write (WP), take respective reference values reduces jitter in the read pointer (RP) by comparing at the instant at which the write pointer (WP) takes the write reference value it leads or lags by one write clock cycle (WCK) with respect to previous periods and, in the event this reference is increased or decreased in the same number of units, so that there is no abrupt change in the direct current component of the output signal of the phase detector (PHC); instead gradually and in fractions of the read reference, it is incremented or reduced in order to produce a smooth variation in the frequency of the read clock (RCK) that compensates the differences in net data output and input streams of the elastic memory (EM).

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"Jitter in Digital Transmission Systems", P. Trischitta et al, Artech House, ISBN 0-89006-248-X, chapter 5, pp. 103-139.

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