Jitter reduction circuit

Details Jitter reduction circuit Jitter reduction circuit

2011-08-30

2011-08-30

Wang, Albert (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C333S020000, C333S164000

Reexamination Certificate

active

08010825

ABSTRACT:
A jitter reduction circuit includes a signal line transmitting a first signal and having a plurality of sections, and a plurality of delay lines transmitting a second signal and provided in one-to-one correspondence to the sections of the signal line, wherein the plurality of delay lines is configured such that a delay of the second signal on a given one of the delay lines is set to a first delay in response to a first level of the first signal in a corresponding one of the sections, and is set to a second delay in response to a second level of the first signal in the corresponding one of the sections.

REFERENCES:
patent: 4855696 (1989-08-01), Tan et al.
patent: 6768342 (2004-07-01), Greenstreet et al.
patent: 7532083 (2009-05-01), Hannah
patent: 2001-044976 (2001-02-01), None

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