Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-08-21
2004-11-16
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S372000, C375S377000
Reexamination Certificate
active
06819725
ABSTRACT:
TECHNICAL FIELD
This invention pertains to minimization of low frequency jitter during bit stuff mapping of plesiosynchronous data signals into synchronized data signals.
BACKGROUND
“Bit stuffing” is a well known technique used in synchronizing data signals by “mapping” such signals from one data rate to a different data rate. For example, as shown in
FIG. 1
, plesiosynchronous signals such as DS-1, DS-2 or DS-3 signals respectively characterized by 1.544 Mb/s, 6.312 Mb/s or 44.736 Mb/s clock rates are commonly mapped from a plesiosynchronous link to a SONET/SDH link having a different characteristic clock rate such as the 1.728 Mb/s rate of the SONET VT1.5 signal. An electronic device known as a “mapper” performs the mapping operation. After transmission over the SONET/SDN link, the signal is desynchronized (demapped) by a demapper which reconverts the SONET/SDH signal to a plesiosynchronous signal for transmission over another plesiosynchronous link.
The bit stuffing technique involves insertion (“stuffing”) of positive or negative bits into the data stream during the mapping operation. If these bit “stuffs” are performed in a regular and efficient manner they impose unacceptable low frequency jitter on the mapped data stream. It is very difficult to remove such low frequency jitter when the data stream is desynchronized (“demapped”), particularly in older “legacy” systems utilizing 40 Hz jitter filters. Consequently, the prior art has evolved various bit stuffing techniques for minimizing low frequency jitter by translating jitter energy to higher frequencies at which it is more easily removed.
One prior art technique utilizes phase lock loops (PLLs) incorporating voltage controlled oscillators (VCOs) having frequency characteristics governed by the level of the FIFO buffer (sometimes called an “elastic store”) through which the data stream is processed. However, VCO-based PLL techniques involve comparatively expensive analog circuitry. In another prior art technique known as “threshold modulation”, the sawtooth-like characteristic of the FIFO buffer fill level is monitored and used to perform dithering of the bit stuffing operation. However, this requires monitoring of the FIFO buffer depth, and access to the FIFO buffer pointers. Moreover, the frequency of the aforementioned sawtooth characteristic affects the higher frequency band into which the jitter energy is translated, constraining circuit design if the sawtooth frequency is fixed.
The present invention addresses the foregoing problems.
SUMMARY OF INVENTION
The invention utilizes a phase lock control loop containing a “delta-sigma” (&Dgr;-&Sgr;) modulator which functions as a VCO to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the data stream is desynchronized (demapped). The modulator generates an accurate pulse train which a mapper incorporating the modulator interprets as stuff
ull/de-stuff commands in such a manner that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.
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Carr Larrie
Oliver Gordon Robert
Bocure Tesfaldet
Oyen Wiggs Green & Mutala
PMC-Sierra Inc.
Tran Khanh
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