Jitter free instruction execution

Details Jitter free instruction execution Jitter free instruction execution

1997-12-12

2000-04-04

Pan, Daniel H.

Electrical computers and digital data processing systems: input/

Interrupt processing

Programmable interrupt processing

710260, 710264, 712241, 712245, G06F 938, G06F 946, G06F 930

Patent

active

060473517

ABSTRACT:
A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

REFERENCES:
patent: 5142634 (1992-08-01), Fite et al.
patent: 5161226 (1992-11-01), Wainer
patent: 5287467 (1994-02-01), Blaner et al.
patent: 5303378 (1994-04-01), Cohen
patent: 5511219 (1996-04-01), Shimony et al.

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