Jitter estimation for a phase locked loop

Details Jitter estimation for a phase locked loop Jitter estimation for a phase locked loop

2002-02-14

2004-11-16

Callahan, Timothy P. (Department: 2816)

Oscillators

Combined with particular output coupling network

C375S371000

Reexamination Certificate

active

06819192

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system (
10
) has, among other components, a microprocessor (
12
), one or more forms of memory (
14
), integrated circuits (
16
) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (
19
), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (
10
).
In order to properly accomplish such tasks, the computer system (
10
) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (
18
) generates a system clock signal (referred to and known in the art as “reference clock” and shown in
FIG. 1
as sys_clk) to various parts of the computer system (
10
). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor (
12
) and the other components of the computer system (
10
) use a proper and accurate reference of time.
One component used within the computer system (
10
) to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., “chip clock,” is a type of clock generator known as a phase locked loop, or “PLL” (
20
). The PLL (
20
) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a system signal. Referring to
FIG. 1
, the PLL (
20
) has as its input the system clock, which is its reference signal, and outputs a chip clock signal (shown in
FIG. 1
as chip_clk) to the microprocessor (
12
). The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL (
20
). This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor (
12
) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (
20
), however, the operations within the computer system (
10
) become non-deterministic.
FIG. 2
shows a PLL (
20
). The PLL (
20
) comprises a feedback loop that aligns the transition edge and frequency of the system clock (
41
) and a feedback loop signal (
40
). The PLL adjusts the output frequency in order to zero any phase and frequency difference between the system clock (
41
) and the feedback loop signal (
40
). The addition of a divide by N circuit (
39
) in the feedback loop enables the PLL to multiple the system clock (
41
). Multiplying the system clock is useful when the chip clock (
42
) must have a higher frequency than the system clock (
41
). The PLL core (
36
) adjusts the output frequency in order to zero any phase and frequency difference between the system clock (
41
) and the feedback loop signal (
40
). By adding the divide by N block (
39
), the chip clock (
42
) must be N times faster to allow the phase and frequency difference between the system clock (
41
) and the feedback loop signal (
40
) to zero. The PLL (
20
) may also have buffers (
37
,
38
) to drive a larger resistive and/or capacitive load. The buffers (
37
,
38
) are in the feedback loop so that the delay created by the buffers (
37
,
38
) is zeroed by the PLL core (
36
).
One common performance measure for a PLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, in a repeated output pattern, such as a clock signal, a transition that occurs from one state to another does not happen at the same time relative to other transitions. Jitter is related to power supply noise. For a circuit designer to appropriately design a PLL, a good understanding of the behavior of the system is required.
FIG. 3
shows a section of a typical power supply network (
100
) of a computer system. The power supply network (
100
) may be representative of a single integrated circuit, or “chip”, or equally an entire computer system comprising multiple integrated circuits. The power supply network (
100
) has a power supply (
112
) that provides a power supply line (
114
) and a ground line (
116
) through an impedance network Z
1
(
118
). The impedance network is a collection of passive elements that result from inherent resistance, capacitance, and/or inductance of physical connections. A power supply line (
122
,
123
) and a ground line (
124
,
125
) supply a circuit A (
120
) and circuit B (
126
), respectively. Power supply line (
123
) and ground line (
125
) also supply circuit C (
130
) through another impedance network Z
2
(
128
) and additional impedance networks and circuits, such as impedance network Z
n
(
132
) and circuit N (
134
). The impedance network and connected circuits may be simulated so that the designer can better understand the behavior of how the circuits interact.
Still referring to
FIG. 3
, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may be analog or digital circuits. Also, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may generate and/or be susceptible to power supply noise. For example, circuit C (
130
) may generate a large amount of power supply noise that affects the operation of both circuit B (
126
) and circuit N (
134
). The designer, in optimizing the performance of circuit B (
126
) and circuit N (
134
), requires an understanding of the characteristics of the power supply noise. By understanding the characteristics of the power supply noise, the designer has a foundation on which to use a variety of design techniques to minimize the amount of power supply noise.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for estimating jitter in a phase locked loop comprises inputting a representative power supply waveform having noise into a simulation of the phase locked loop, and estimating jitter of the phase locked loop from the simulation.
According to another aspect of the present invention, a computer system for estimating jitter in a phase locked loop comprises a processor, a memory; and software instructions stored in the memory adapted to cause the computer system to input a representative power supply waveform having noise into a simulation of the phase locked loop, and estimate jitter of the phase locked loop from the simulation.
According to another aspect of the present invention, a computer-readable medium having recorded thereon instructions executable by a processor, the instructions adapted to input a representative power supply waveform having noise into a simulation of a phase locked loop, and estimate jitter of the phase locked loop from the simulation.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5828255 (1998-10-01), Kelkar et al.
patent: 6333905 (2001-12-01), Kobayashi et al.
patent: 6441602 (2002-08-01), Eckhardt et al.
patent: 6460001 (2002-10-01), Yamaguchi et al.
Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops, Keith A. Jenkins and James P. Eckhardt, IEEE Design & Test of Computers, Apr.-Jun. 2000, pp. 86-93.

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