Jitter-detecting circuit, receiving circuit including the...

Details Jitter-detecting circuit, receiving circuit including the... Jitter-detecting circuit, receiving circuit including the...

2003-02-25

2008-10-07

Fan, Cheih M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S362000

Reexamination Certificate

active

07433440

ABSTRACT:
To provide a method for making a receiving-sensitivity control parameter for deciding the receiving sensitivity of an optical receiving circuit automatically follow the optimum position by using the jitter value of a binary-equalizing-data signal obtained by binary-converting an input signal as a parameter showing the quality of the input signal. A binary-equalizing-data signal output from a limiter amplifier and a clock extracted by a clock-extracting circuit are input to a jitter-detecting circuit. The jitter-detecting circuit outputs a voltage corresponding to the jitter value of the binary-equalizing-data signal. A control circuit receives an output of the jitter-detecting circuit and performs an arithmetic processing by using a DSP or the like, and controls the identification voltage of the limiter amplifier so that the jitter value of the binary-equalizing-data signal (output of jitter-detecting circuit) is minimized.

REFERENCES:
patent: 4987298 (1991-01-01), Inagaki
patent: 5473639 (1995-12-01), Lee et al.
patent: 6100724 (2000-08-01), Yoshimura et al.
patent: 6271945 (2001-08-01), Terahara
patent: 6411144 (2002-06-01), Matsuno
patent: 2002/0044325 (2002-04-01), Noguti
patent: 2002/0159672 (2002-10-01), Fells et al.
patent: H3-108832 (1991-05-01), None
patent: H5-225707 (1993-09-01), None

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