Jitter correction method and circuit

Details Jitter correction method and circuit Jitter correction method and circuit

2011-08-16

2011-08-16

Fan, Chieh M (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S516000, C702S069000

Reexamination Certificate

active

08000429

ABSTRACT:
In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data1clock prior to and a head bit of data1clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.

REFERENCES:
patent: 11-163951 (1999-06-01), None
patent: 2003/218843 (2003-07-01), None
patent: 2003/304225 (2003-10-01), None

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