Jitter and skew suppressing delay control apparatus

Details Jitter and skew suppressing delay control apparatus Jitter and skew suppressing delay control apparatus

2007-01-09

2007-01-09

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S191000, C365S194000

Reexamination Certificate

active

11167627

ABSTRACT:
A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.

REFERENCES:
patent: 6836503 (2004-12-01), Best et al.
patent: 2004/0222828 (2004-11-01), Ishikawa

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