JFET structure for integrated circuit and fabrication method

Details JFET structure for integrated circuit and fabrication method JFET structure for integrated circuit and fabrication method

2007-09-11

2007-09-11

Parker, Kenneth (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S287000, C257S504000, C257SE27148, C257SE29265, C257SE21421

Reexamination Certificate

active

11038562

ABSTRACT:
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

REFERENCES:
patent: 4373253 (1983-02-01), Khadder et al.
patent: 4503603 (1985-03-01), Blossfeld
patent: 5296409 (1994-03-01), Merrill et al.
patent: 5618688 (1997-04-01), Reuss et al.
patent: 5670393 (1997-09-01), Kapoor
patent: 5933733 (1999-08-01), Ferla et al.
patent: 6352887 (2002-03-01), Hutter et al.

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