Iterative prediction of circuit delays

Details Iterative prediction of circuit delays Iterative prediction of circuit delays

2000-06-13

2002-09-24

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06457160

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns circuit analysis, and particularly relates to circuit timing analysis, such as for use in designing and fabricating integrated circuits.
2. Description of the Related Art
An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) typically includes cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex interconnections between them.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. An example of a cell is an AND or an OR gate. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has many thousands or millions of pins which must be connected in various combinations, the chip also includes definitions of many thousands or millions of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically on the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected.
A netlist is a complete description of the circuit including cells, connectivity, and netnames.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
In the field of integrated circuit (IC) technology, one of the most important design considerations is the speed in which a particular IC design operates. During the design process, an IC design is analyzed multiple times for its timing characteristics, also called “delay” of the circuit. As IC designs grow increasingly large and complex, performing a delay analysis, or “delay prediction,” may take many hours or days, even on very powerful computers. This is because these large IC designs use many components (such as gates) and because the interconnections between those components often are very complex.
Accordingly, what is needed is a technique for faster delay prediction of a design.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problem by providing an iterative technique in which blocks are specified, and then steps of block and circuit delay calculation based on delay calculation collars (DCCs) and modification of the DCCs based on the delay calculations are repeated.
Thus, the invention is directed to circuit delay prediction in which blocks (preferably, non-overlapping blocks) are specified, each of the blocks including a portion of the circuit. Delay calculation collars (DCCs) are then defined for the blocks, the DCCs including complete dependency information required to calculate delay within the blocks. Next, delay is calculated for the blocks based on the DCCs and delay is calculated for the circuit based on the DCCs. The DCCs are then modified as necessary based on results of either or both of the delay calculation for the blocks or the circuit. The delay calculation and DCC modification steps are then repeated.
By repetitively calculating delay based on DCCs and DCCs based on delay in the foregoing manner, the present invention typically can provide faster delay calculation than conventional techniques would permit. In particular, the foregoing iterative block segmentation allows delay calculation to be performed only for a number of relatively small blocks, which generally will be much faster than attempting to delay predict the entire circuit at once, even after taking the iterations into account.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.


REFERENCES:
patent: 5867399 (1999-02-01), Rostoker et al.

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