Isotropic processor

Details Isotropic processor Isotropic processor

2008-08-29

2010-12-14

Beausoilel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S015000, C714S035000

Reexamination Certificate

active

07853827

ABSTRACT:
The present disclosure is directed toward a method for restoring a computer processor to a previous state. Described is a processor/memory architecture that may store successive instructions/data into a pushdown stack. As instructions are loaded and executed, the loading and executing of new instructions may be suspended. The instruction execution and memory stack then may be restored to a previous processor state in terms of instructions, processor memory state, register values, etc.

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Wu, Kun-Lung, et al., “Error Recovery in Shared Memory Multiprocessors Using Private Caches”, IEEE Transactions on Parallel and Distributed Systems, pp. 231-240, vol. 1, No. 2, Apr. 1990, IEEE.

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