Isolation trench

Details Isolation trench Isolation trench

2006-08-01

2009-11-24

Lindsay, Jr., Walter L (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S328000, C257S329000, C257SE21540, C257SE21430, C438S424000, C438S431000

Reexamination Certificate

active

07622769

ABSTRACT:
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

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Advertisement entitled “Polysilazane SODs Spinfil™ 400 Series for STI/PMD Application.”
Peters, Laura, “Choices and challenges for shallow trench Isolation,” Semiconductor International, Website www.ree-electronics.com, Apr. 1, 1999, 6 pages.

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