Isolation technology for submicron semiconductor devices

Details Isolation technology for submicron semiconductor devices Isolation technology for submicron semiconductor devices

2000-02-16

2004-04-27

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S439000, C438S445000, C438S452000

Reexamination Certificate

active

06727161

ABSTRACT:

BACKGROUND OF THE INVENTION
The present relates to an isolation technology for semiconductor devices.
A variety of methods and structures have been used to isolate areas on semiconductor devices. One conventional technology is based on localized oxidation of silicon (LOCOS), shown in FIG.
1
. In
FIG. 1
, on the silicon substrate
102
is a field oxide
104
that acts to isolate an active area of the semiconductor device; the field oxide is contiguous with the gate oxide
110
on the active region of the silicon substrate. The active area in this illustration includes a layer of silicon nitride
106
. The field oxide encroaches on the active area in the shape of a bird's beak
108
, before narrowing into the gate oxide. This large encroachment distorts the active region, and interferes with the submicron lithography necessary to construct elements in the active region.
Another widely used isolation technique is silicon trench isolation (STI), shown in FIG.
2
. The field oxide
104
does not have the shape of a bird's beak where it narrows into the gate oxide
110
on the silicon substrate
102
. FIGS.
3
(
a
)-
3
(
e
) illustrate the step used to prepare the structure shown in FIG.
2
. In FIG.
3
(
a
) thermal oxidizing forms a thermal oxide layer
111
on the silicon substrate
102
, followed by depositing a silicon nitride layer
106
using low pressure chemical vapor deposition (LPCVD). In FIG.
3
(
b
) a photoresist layer
112
is applied, and patterned using a mask. Etching of those portions of the silicon nitride, thermal oxide and silicon substrate not covered by the photoresist layer, in a single operation, opens a trench
114
.
In FIG.
3
(
c
) the photoresist layer is first stripped, and the substrate is cleaned. A thin oxide layer
118
is then grown by dry oxidation of the exposed portions of the silicon substrate. An oxide layer
116
is then deposited into the trench and across the surface of the structure by chemical vapor deposition (CVD). In FIG.
3
(
d
) chemical-mechanical polishing (CMP) planarizes the surface, leaving the oxide layer
116
only in the trench. In FIG.
3
(
e
) the silicon nitride and thermal oxide layers are removed, and a gate oxide layer
110
is grown on the silicon substrate.
In the STI process described above, silicon etching is usually performed by reactive ion etching (RIE), which may result in damage to the etched area. The damage may create defects, contamination and stress that may result in electrical degradation of the device, such as high leakage and low efficiency isolation performance.
Often the STI process will include thermal treatments such as thermal oxidation and annealing or densification to remove the defects. However, these treatments are frequently insufficient to obtain a damage-free silicon surface in the trench, and may lead to even greater damage at the lower corners of the trench oxide structures (e.g., dislocations in the surrounding silicon) due to greater thermal expansion of oxide relative to silicon. The upper corners of the trench (and the adjacent silicon) also experience problems resulting from a similar stress concentration, as well as an increased risk of electrical “leakage” from local electric field effects.
CVD of oxide into the trench may also exacerbate the defect problems, possibly by aggregating contamination from the oxide at the defects in the silicon surface during annealing or densification, and/or by bearing the stress from the silicon corners.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the present invention concerns a process for making a semiconductor structure, including forming a dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes (a) a semiconductor substrate having the regions, (b) a first dielectric layer, on at least a second region of the semiconductor substrate, (c) an etch-stop layer, on at least a portion of the dielectric layer, and (d) spacers on at least a third region of the semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.
In a second aspect, the present invention concerns a semiconductor structure, including: (i) a semiconductor substrate, (ii) field oxide regions on a first portion of the semiconductor substrate, and (iii) gate oxide regions on a second portion of the semiconductor substrate. The surface of the first portion of the semiconductor substrate does not contain reactive ion etch damage.
Definitions
A thick dielectric layer is a dielectric layer (for example, a silicon oxide layer or silicon nitride layer) that has a thickness greater than the thickness of a thin dielectric layer, and preferably has a thickness of 1000 to 50,000 Å, more preferably a thickness of 5000 to 10000 Å.
A thin dielectric layer is a dielectric layer (for example, a silicon oxide layer or silicon nitride layer) that has a thickness less than the thickness of a thick dielectric layer, and preferably has a thickness of 10 to 999 Å, more preferably a thickness of 100 to 250 Å.
The term “adjacent” means that there are no functional structures between the specified structures. A functional structure is a structure intentionally placed on the semiconductor device that affects the function of the device. For example, a functional structure may mean a structure having a predetermined set of dimensional and/or compositional parameter values, that has an electrical, mechanical and/or optical function (e.g., conductive, insulative, masking, photolithographic, antireflective).
The term “exposed regions” means regions of a structure that are not covered by another structure.
The term “planarizing” means to flatten, level or remove material, preferentially in the vertical direction, to enhance the planarity of the structure.
The term “reactive ion etch damage” means damage associated with reactive ion etching that can affect the performance of a semiconductor device containing such damaged areas.
The term “oxide” refers to a metal oxide conventionally used to isolate electrically active structures in an integrated circuit from each other, typically an oxide of silicon and/or aluminum (e.g., SiO
2
or Al
2
O
3
, which may be conventionally doped with fluorine, boron, phosphorous or a mixture thereof; preferably SiO
2
or SiO
2
conventionally doped with 1-12 wt. % of phosphorous and 0-8 wt. % of boron).


REFERENCES:
patent: 4764248 (1988-08-01), Bhattacherjee et al.
patent: 4842675 (1989-06-01), Chapman et al.
patent: 4892614 (1990-01-01), Chapman et al.
patent: 4965221 (1990-10-01), Dennison et al.
patent: 5096848 (1992-03-01), Kawamura
patent: 5298451 (1994-03-01), Rao
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5326715 (1994-07-01), Jang et al.
patent: 5374585 (1994-12-01), Smith et al.
patent: 5413953 (1995-05-01), Chien et al.
patent: 5445990 (1995-08-01), Yook et al.
patent: 5472905 (1995-12-01), Paek et al.
patent: 5652177 (1997-07-01), Pan
patent: 5674775 (1997-10-01), Ho et al.
patent: 5683933 (1997-11-01), Seino
patent: 5686346 (1997-11-01), Duane
patent: 5696022 (1997-12-01), Jang
patent: 5705422 (1998-01-01), L'Yee
patent: 5731221 (1998-03-01), Kwon
patent: 5731241 (1998-03-01), Jang et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5807789 (1998-09-01), Chen et al.
patent: 5811345 (1998-09-01), Yu et al.
patent: 5811347 (1998-09-01), Gardner et al.
patent: 5824594 (1998-10-01), Kim et al.
patent: 5834360 (1998-11-01), Tesauro et al.
patent: 5849625 (1998-12-01), Hsue et al.
patent: 5849626 (1998-12-01), Song
patent: 5851901 (1998-12-01), Gardner et al.
patent: 5891787 (1999-04-01), Gardner et al.
patent: 5910018 (1999-06-01), Jang
patent: 5918131 (1999-06-01), Hsu et al.
patent: 5920787 (1999-07-01), Haskell et al.
patent: 5926722 (1999-07-01), Jang et al.
patent: 5937309 (1999-08-01), Chuang
patent: 5940719 (1999-08-01), Jang et al.
patent: 5945352 (1999-08-01), Chen et al.
patent: 5945724 (1999-08-01), Parekh et al.
patent: 5972778 (1999-10-01), Hamada
patent: 5981354 (1999-11-01), Spikes et al.
patent: 5998278

Affiliated with

Also associated with

Rating

Isolation technology for submicron semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation technology for submicron semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation technology for submicron semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3230962