Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2009-04-15
2011-12-06
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S447000, C438S452000
Reexamination Certificate
active
08071455
ABSTRACT:
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.
REFERENCES:
patent: 4416050 (1983-11-01), Sarace
patent: 4760273 (1988-07-01), Kimata
patent: 5251019 (1993-10-01), Moorman et al.
patent: 5501990 (1996-03-01), Holm et al.
patent: 6177333 (2001-01-01), Rhodes
patent: 6204524 (2001-03-01), Rhodes
patent: 6225171 (2001-05-01), Yu et al.
patent: 6372603 (2002-04-01), Yaung et al.
patent: 6380037 (2002-04-01), Osanai
patent: 6545302 (2003-04-01), Han
patent: 6720595 (2004-04-01), Clevenger et al.
patent: 6767759 (2004-07-01), Rhodes
patent: 6888214 (2005-05-01), Mouli et al.
patent: 6930336 (2005-08-01), Merrill
patent: 7400004 (2008-07-01), Cole et al.
patent: 2001/0023949 (2001-09-01), Johnson et al.
patent: 2003/0089929 (2003-05-01), Rhodes
patent: 2003/0127667 (2003-07-01), Inoue et al.
patent: 2003/0209743 (2003-11-01), Park
patent: 2004/0075110 (2004-04-01), Yaung et al.
patent: 2004/0178430 (2004-09-01), Rhodes et al.
patent: 2004/0188727 (2004-09-01), Patrick
patent: 2004/0195592 (2004-10-01), Fossum
patent: 2004/0227061 (2004-11-01), Clevenger et al.
patent: 2005/0017316 (2005-01-01), Yaung
patent: 2005/0045926 (2005-03-01), Mouli
patent: 2005/0061978 (2005-03-01), Ilda et al.
patent: 2005/0121708 (2005-06-01), Hong
patent: 2005/0133825 (2005-06-01), Rhodes et al.
patent: 2005/0176167 (2005-08-01), Lee
patent: 2005/0184353 (2005-08-01), Mouli
patent: 0 077 156 (1983-04-01), None
patent: 63009968 (1988-01-01), None
Mendis, et al., “CMOS Active Pixel Image Sensor”, IEEE Transactions on Electron Devices, vol. 41, No. 3, Mar. 1994, pp. 452-453.
Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2046-2050.
Cole Bryan G.
Sorensen Troy
Aptina Imaging Corporation
Perkins Pamela E
Smith Zandra
Tsai Jason
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