Isolation structure of a shallow semiconductor device trench

Details Isolation structure of a shallow semiconductor device trench Isolation structure of a shallow semiconductor device trench

1997-02-11

1999-02-09

Fourson, George

Metal treatment

Barrier layer stock material, p-n type

With non-semiconductive coating thereon

257513, 438424, H01L 2176

Patent

active

058688706

ABSTRACT:
A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

REFERENCES:
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4549927 (1985-10-01), Goth et al.
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4582565 (1986-04-01), Kawakatsu
patent: 4661832 (1987-04-01), Lechaton et al.
patent: 4729006 (1988-03-01), Dally et al.
patent: 4740480 (1988-04-01), Ooka
patent: 4853344 (1989-08-01), Darmawan
patent: 4952524 (1990-08-01), Lee et al.
patent: 4985368 (1991-01-01), Ishii et al.
patent: 5059550 (1991-10-01), Tateoka et al.
patent: 5168076 (1992-12-01), Godohino et al.
patent: 5213994 (1993-05-01), Fuchs
patent: 5229315 (1993-07-01), Jun et al.
patent: 5229317 (1993-07-01), Nishio
patent: 5281550 (1994-01-01), Ducreux
patent: 5306940 (1994-04-01), Yamazaki
patent: 5384280 (1995-01-01), Aoki et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5468676 (1995-11-01), Madan
patent: 5506168 (1996-04-01), Morita et al.
patent: 5576241 (1996-11-01), Sakai
"The Inverse-Narrow-Width Effect", Lex A. Akers, IEEE Electron Device Letters, vol. EDL-7, No. 7, Jul. 1986, pp. 419-421.
"Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow Width Effect of N-Mos Threshold Voltages", Fuse et al., Semiconductor Research Center, Matsushita Eelectric Industrial Co., V1-2, pp. 58-59.
"A Practical Trench Isolation Technology with a Novel Planarization Process", Fuse et al., Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd 3-15, 1987 IEEE, pp. 732-735.
"A Simplified Box (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories", Shibata et al., Toshiba Research and Development Center, 1983 IEEE pp. 27-30.
"A Variable-Size Shallow Trency Isolation (STI) Technology with Diffused Sidewall Doping For Submicron CMOS", Davari et al., IBM T.J. Watson Res. Center, 1988 IEEE, pp. 92-95.
"A New Planarization Technique, Using a Combination of Rie and Chemical Mechanical Polish (CMP)", Davari et al, IBM Research, T.J. Watson Res. Center, 1989 IEEE, pp. 61-64.
"A New Three-Dimensional Mosfet Gate-Induced Drain Leakage Effect in Narroy Deep Submicron Devices", Geissler et al., IBM General Technology Division, 1991 IEEE, pp. 839-842.
IBM Technical Disclosure Bulletin, vol. 31, No. 7, pp. 178-179, Dec. 1988.

Affiliated with

Also associated with

Rating

Isolation structure of a shallow semiconductor device trench does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation structure of a shallow semiconductor device trench, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation structure of a shallow semiconductor device trench will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1945874