Isolation structure and method

Details Isolation structure and method Isolation structure and method

1999-06-17

2001-01-30

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S425000, C257S506000

Reexamination Certificate

active

06180491

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor structures and fabrication techniques and more particularly to an isolation structure and method for forming the same.
BACKGROUND OF THE INVENTION
The isolation of semiconductor devices fabricated on a wafer or substrate has traditionally been performed using local oxidation of substrate (“LOCOS”) isolation techniques in both bulk silicon substrate applications and silicon-on-insulator (“SOI”) substrate applications. More recently, device isolation Is being performed using trench isolation such as shallow trench isolation in bulk silicon substrate applications and mesa isolation in SOI substrate applications. Trench isolation provides advantages in both bulk substrate applications and SOI substrate applications. Trench isolation appears to provide even greater advantages in SOI substrate applications due to the ability to achieve isolation with a relatively shallow trench.
Although trench isolation techniques provide significant advantages, along with these advantages come certain problems and disadvantages. Specifically, when attempting to isolate an area, such as a gate junction or channel in a field-effect transistor or metal-oxide semiconductor field-effect transistor (“MOSFET”), from other devices or regions using trench isolation technology, the threshold voltage (“V
t
”) is lowered due to the presence of a parasitic transistor at the edge or corner where a trench wall meets the edge of the transistor. Furthermore, the gate oxide integrity (“GOI”) is often degraded. These problems, present in both bulk silicon substrate applications and SOI substrate applications, are caused by the compressive thinning of the gate oxide and the two-dimensional field-effects at the top corner or edge where the trench wall meets the edge of the transistor. The lower threshold voltage V
t
of the parasitic transistor is caused by the sharp corner or edge which allows leakage currents to flow before the threshold voltage V
t
of the main transistor is reached. The sharp corner or edge has a relatively small radius of curvature which decreases the threshold voltage V
t
of the parasitic transistor. The GOI is compromised because of the compressive thinning of the gate oxide that forms around the top corner or edge where the trench wall meets the edge of the transistor or MOSFET. This thinning region has a lower breakdown voltage which decreases overall device reliability.
The presence of the parasitic transistor with the low threshold voltage V
t
produces excessive or higher off-state leakage currents which substantially increases overall power consumption. The off-state leakage currents also result in excess heat generation and cause problems related to the dissipation of this excess heat. GOI degradation impairs and reduces overall system or chip reliability.
SUMMARY OF THE INVENTION
From the foregoing it may be appreciated that a need has arisen for an isolation structure and method for forming the same that eliminate or reduce the problems and disadvantages described above. In accordance with the present invention, an isolation structure and method are provided that prevent the formation of a parasitic transistor with a threshold voltage V
t
that is less than the threshold voltage V
t
of a main transistor device. The present invention reduces or eliminates off-state leakage currents and increases the GOI to improve overall system reliability in the fabrication of MOSFETs, BiCMOS circuits, isolated gate bipolar transistors, and virtually any device having a sharp corner or edge where an active region meets the trench wall of a trench region. The present invention may be used when shallow trench isolation techniques are used in bulk silicon substrates and when mesa isolation techniques are used in SOI substrates.
According to an embodiment of the present invention, an isolation structure is provided that includes a substrate, a refill material, a gate dielectric layer, and a gate conductor layer. The substrate has a first active region, a second active region, and a trench region having trench walls and which is positioned between the first active region and the second active region. The first active region has a top corner or edge that is provided where an upper surface of the first active region meets with the trench wall of the trench region that is adjacent to the first active region. The refill material is positioned within the trench region and extends to cover at least a portion of the top corner. The gate dielectric layer is provided on the upper surface of the first active region, while the gate conductor layer is provided on an upper surface of the gate dielectric layer.
The present invention provides various technical advantages. A technical advantage of the present invention includes the reduction or elimination of off-state leakage currents. Another technical advantage of the present invention includes decreased heat dissipation and power consumption. Still another technical advantage of the present invention includes the prevention of the formation of a parasitic transistor with a threshold voltage V
t
that is less than the threshold voltage V
t
of a main transistor device such as a MOSFET. Yet another technical advantage includes increased gate oxide integrity which improves overall system and chip reliability. Other technical advantages are readily apparent to one skilled in the art from the following FIGURES, description, and claims.


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