Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-04-15
2008-04-15
Purvis, Sue A. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S401000, C257S616000, C257S900000, C257SE27112
Reexamination Certificate
active
07358571
ABSTRACT:
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
REFERENCES:
patent: 5482871 (1996-01-01), Pollack
patent: 6017801 (2000-01-01), Youn
patent: 6048756 (2000-04-01), Lee et al.
patent: 6064090 (2000-05-01), Miyamoto et al.
patent: 6509583 (2003-01-01), Iwamatsu et al.
patent: 6555879 (2003-04-01), Krivokapic et al.
patent: 6566198 (2003-05-01), Park et al.
patent: 6596615 (2003-07-01), Ipposhi et al.
patent: 6642115 (2003-11-01), Cohen et al.
patent: 6653656 (2003-11-01), Iwamatsu et al.
patent: 6774390 (2004-08-01), Sugiyama et al.
patent: 6838733 (2005-01-01), Takehiro
patent: 6963114 (2005-11-01), Lin
patent: 6967377 (2005-11-01), Cohen et al.
patent: 7091071 (2006-08-01), Thean et al.
patent: 2004/0222463 (2004-11-01), Yeo et al.
Richard C. Jaeger, Introduction to Microelectronic Fabrication, 2002, Prentice Hall, vol. 5, 1 and 163.
Hongmei Wang et al., The Behavior of Narrow-Width SOI MOSFET's With MESA Isolation, Mar. 2000, pp. 593-600, vol. 47, No. 3, IEEE Transactions on Electron Devices, 0018-9383/00.
Choi, Yang-Kyu, et al., “30nm Ultra-Thin-Body SOI MOSFET with Selectively Deposited Ge Raised S/D”, Device Research Conference, Jun. 2000, pp. 23-24, Denver, CO.
Leland, Chang, et al., “Moore's Law Lives On”, IEEE Circuits & Devices Magazine, Jan. 2003, pp. 35-42.
Ke Chung-Hu
Ko Chih-Hsin
Lee Wen-Chin
Yeo Yee-Chia
Haynes & Boone LLP
Purvis Sue A.
Rodela Eduardo A.
Taiwan Semiconductor Manufacturing Company
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