Isolation-region configuration for integrated-circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S501000, C257S506000, C257S524000, C257S374000, C257S446000, C257S725000

Reexamination Certificate

active

07122876

ABSTRACT:
A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

REFERENCES:
patent: 4878096 (1989-10-01), Shirai et al.
patent: 6025628 (2000-02-01), Lee et al.
patent: 6376296 (2002-04-01), Tung
patent: 2004/0033666 (2004-02-01), Williams et al.
patent: 2005/0064670 (2005-03-01), Pan et al.

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