Isolation of memory cells in cross point arrays

Details Isolation of memory cells in cross point arrays Isolation of memory cells in cross point arrays

2001-07-26

2002-10-08

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S209000, C257S262000

Reexamination Certificate

active

06462388

ABSTRACT:

TECHNICAL FIELD
The technical field is memory cells for cross point memory arrays. More specifically, the technical field is memory cells having an isolation feature built into the memory cells.
BACKGROUND
Cross point memory arrays include horizontal word lines that cross vertical bit lines. Memory cells are located at the cross points of the word and bit lines, and function as the storage elements of a memory array. The memory cells each store a binary state of either “1” or “0.” A selected memory cell can have its binary state changed by applying write currents to the word line and the bit line that cross at the selected memory cell. The binary state of a selected memory cell is read by applying a read voltage to the memory cell, and by measuring the resistance across the memory cell from the current passing through the memory cell.
A cross point memory array may have all memory cells connected together as one large parallel circuit. Ideally, current passes only through a selected memory cell during a read operation. However, in a large parallel circuit memory array, currents flow through unselected memory elements during read operations. These currents are referred to as “sneak path currents.” If the cross point memory array has a high density of memory cells, neighboring memory cells must be isolated from one another so that a selected memory cell is not affected by sneak path currents during a read operation.
Conventional parallel-connected cross point arrays include a control device in series with each memory cell to prevent sneak path currents. One conventional control device is a series MOS transistor located in a memory cell. The series MOS transistor is controlled by the word line connected to the memory cell. The series MOS transistor isolates the selected memory cell from unselected memory cells in the memory array by breaking parallel connections of memory cells. During read operations, only the MOS transistor in the selected memory cell is turned on. The MOS transistors in unselected cells are turned off, thereby preventing sneak path currents from flowing through unselected memory cells.
A disadvantage to MOS transistors is that they consume valuable substrate area, and the memory cells must be larger in order to accommodate electrical contacts from the memory cell to the substrate.
Another way to prevent sneak path currents is to place a series diode in a substrate of a memory array, or in plane with the memory cells of the memory array. This isolates the memory cells, but the associated diode forward voltage drops are large. A large forward voltage drop negatively affects the ability to read and write data in the memory cells.
A need therefore exists for an isolation feature for a memory cell that does not occupy substrate area, and that does not negatively affect the ability to read or write the memory cell
SUMMARY
According to a first aspect, a memory array includes memory cells located at cross points of first and second conductors. The memory cells are compound structures that are capable of storing data, and of isolating the memory cells from sneak path currents.
The memory cells include tunnel gate surface effect transistors having non-uniform gate oxides. The gate oxides are supported on pillar diode structures. A memory cell stores a binary state in a tunnel junction of the gate oxide. In addition, a control gate of the transistor disconnects the tunnel junction from sidewalls of the pillar, preventing current flow through the memory cell. The control gate therefore prevents sneak path currents through the memory cell.
According to the first aspect, the gate oxide provides an isolation feature to a memory cell that does not require space on the substrate. This allows more memory cells to be placed on the substrate, increasing array density.
In addition, the memory cells have a low forward voltage drop. Low forward voltage drops enhance the ability to sense the binary states of the memory cells, improving the ability to read the memory array.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures.


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