Isolation method of semiconductor device

Details Isolation method of semiconductor device Isolation method of semiconductor device

1990-11-13

1992-08-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 63, H01L 2176

Patent

active

051418843

ABSTRACT:
An isolation method of semiconductor devices comprises the steps of forming a multilayer, defining both active and isolating regions, forming a channel stopper, removing the multilayer on a nitride layer to form a capping oxide layer, removing the multilayer on the nitride layer and a polysilicon layer to form an isolation layer, forming spacers at sidewalls of the isolation region, forming a gate oxide layer and a gate oxide electrode, and forming a second conductive diffusion regions, wherein the CVD process and photolithography methods are applied in formation of the isolating layer not to result in the bird's beak and dislocation caused by stress and the channel stopper is formed by ion-implantation of impurity without its diffusion not to contact with the isolating layer by the spacers on the sidewalls thereof in its diffusion region which is formed by the ion-implantation. Therefore, according to the present invention, the limit of the isolation can be extended into a sub-micron range so as to prevent the narrow channel effect and increase the breakdown voltage.

REFERENCES:
patent: 4818235 (1989-04-01), Chao

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