Isolation for SOI chip with multiple silicon film thicknesses

Details Isolation for SOI chip with multiple silicon film thicknesses Isolation for SOI chip with multiple silicon film thicknesses

2005-04-12

2005-04-12

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S623000, C257S500000, C257S501000, C257S506000, C257S524000

Reexamination Certificate

active

06879000

ABSTRACT:
A semiconductor-on-insulator chip is provided which includes a substrate that is formed of an electrically insulating material; a semiconducting layer overlying the substrate; a first region in the semiconducting layer that has a first thickness, the first region includes silicon regions defined by a shallow trench isolation; and a second region in the semiconducting layer that has a second thickness, the second region includes active regions defined by mesa isolation.

REFERENCES:
patent: 5973358 (1999-10-01), Kishi
patent: 6060748 (2000-05-01), Uchida et al.
patent: 6114197 (2000-09-01), Hsu
patent: 6448114 (2002-09-01), An et al.
patent: 6548369 (2003-04-01), van Bentum

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