Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-13
2001-04-17
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000
Reexamination Certificate
active
06218286
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates specifically to chemical-mechanical polishing (CMP) methods used to planarize device wafers having multiple levels of polysilicon layers sandwiched between insulating layers.
(2) Background of the Invention & Description of Prior Art
In the development of the integrated circuits (IC), the industry is ever striving to improve performance by scaling down the device dimensions for high speed circuits. However, scaling down the device has arrived at a point that further scaling is less profitable due to the high risk of yield and reliability failures. Eventually, the down-sizing of the active device have become less expedient in improving the performance further, without exponentially increasing the cost of fabrication by the IC manufacturers. Thereby, the manufacturers of the IC industry seek other alternatives to increase the circuit speed and maximum functional density and complexity by improving the interconnects. The predominant method to circumvent the aforementioned limitations involves the adaptation of vertical stacking of integrated devices and interconnect wiring levels.
The switch to multilevel interconnection for performance advantage causes loss of topographical planarity. The resulting non-planar topography of the device wafer in turn creates problems in photolithography, etching, as well as electrical shorts and many other related problems. One of the current state-of-the-art methods to planarize the non-planar surface of device wafer is by the chemical-mechanical polishing (CMP) technique.
Doan & Meikle in U.S. Pat. No. 5,395,801 have describe a method for planarizing a semiconductor wafer having non-planar topography by the deposition of a conformal layer of insulating material of a first thickness to the wafer. A CMP protective layer of different composition and thickness than the conformal insulating layer is deposited over the conformal layer. The CMP polishing of both protective and underlying conformal insulating layers is done with a single CMP step using a single CMP slurry and under conditions which in combination with the slurry removes the conformal layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal insulating layer in high topographical areas restricting material removal from low topographical areas during this CMP process. Doan & Meikle further described other alternatives to the aforementioned sing slurry CMP process by using two or three CMP steps with respective CMP slurries and different selective polishing rates
This invention will describe a CMP process to address the problems of multi-level polysilicon to polysilicon shorts due to conventional CMP planarization of the non-planar surface of semiconductor device wafer, by deposition of another insulating layer after the chemical-mechanical polishing before depositing the next polysilicon layer.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a process to planarize semiconductor device wafers having several levels of interconnects, such as multi-level polysilicon layers sandwiched between the insulating layers.
It is another object of this invention to use the one step CMP polishing process with a single slurry as the planarization process.
It is still another object of this invention to prevent interlevel polysilicon to polysilicon shorts by depositing a second insulating layer after chemical-mechanical polishing and planarizing the first insulating layer.
In accordance with the present invention a process is described to planarize a non-planar semiconductor device wafer having multi-levels of polysilicon contacts and wirings. An insulating layer such as oxide from tetraethylorthosilicate source (TEOS) is deposited over a semiconductor wafer with non-planar topography surface. The semiconductor device wafer is then subjected to the chemical-mechanical polishing (CMP) processing using a single polishing slurry. Due to the non-uniform polishing rate at the high and low spots in the surface topography the resulting surfaces after CMP polishing invariably show that some of the surfaces of the polysilicon in the high topographical areas are exposed without insulating coverage. A second oxide material layer of sufficient thickness is deposited over the entire wafer to insure that the exposed polysilicon surfaces in the high topographical regions and edges are covered with this second insulating layers. Another level of polysilicon is deposited over this second insulating layer and patterned by the conventional photolithographic and dry or wet etching procedures.
REFERENCES:
patent: 5395801 (1995-03-01), Doan et al.
patent: 6001731 (1999-12-01), Su et al.
Liang Mong-Song
Su Chung-Hui
Wang Chen-Jong
Wuu Shou-Gwo
Ackerman Stephen B.
Booth Richard
Saile George O.
Taiwan Semiconductor Manufacturing Company
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