Isolating circuit for P/N transmission gate during hot-plug...

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C326S081000, C326S027000

Reexamination Certificate

active

06670829

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to hot plugging isolation circuits, and more particularly to control circuits for bus switches for live insertion when the bus switch is powered down.
High-speed communication systems often are used to connect computer users together. Networks allow users to share data and work cooperatively.
At a physical level, these networks have cables that connect together user's stations, and these cables are in turn connected together using relays or switches. Traditional electromechanical relays are being replaced by solid-state relays and transmission-gate bus switches.
Bus switches are semiconductor integrated circuits (IC's) that use metal-oxide semiconductor (MOS) transistors to make or break the connection. Several switches may be combined on a single silicon die. One such device is made by the assignee and marketed as the P15C3861 Bus Switch. More background on bus switches can be found in Parallel Micro-Relay Bus Switch for Computer Network Communication with Reduced Crosstalk and Low On-Resistance using Charge Pumps, U.S. Pat. No. 5,808,502, also “Bus Switch Having Both P- and N-Channel Transistors for Constant Impedance Using Isolation Circuit for Live-Insertion when Powered, U.S. Pat. No. 6,034,553.
FIG. 1
shows a prior-art bus switch device. N-channel transistor
10
conducts current from its drain to its source, connecting signal lines from two buses when an enable signal is applied to the gate of n-channel transistor
10
. Bus switches are usually large in size to allow a large amount of current to flow, and to provide a low on resistance.
While such an NMOS bus switch is effective for 5-volt systems, newer 3-volt systems have lower noise margins. When the gate of n-channel transistor
10
is driven to the 3-volt power supply, a voltage drop of a threshold voltage occurs across the channel. Thus a 3-volt signal applied to the drain of transistor
10
is degraded to a 2-volt signal at its source. Other devices on the bus may require TTL input-voltages. These TTL devices require a high voltage of at least 2.0 volts, leaving no noise margin for voltage drops across the bus.
Future reductions in supply voltage may make the use of simple NMOS bus switches impossible. One solution is to use a charge pump or DC—DC converter to generate a boosted voltage above the 3-volt supply, and to apply this boosted voltage to the gate of the NMOS bus switch. Such DC—DC converters draw current and may not be able to meet speed requirements.
A p-channel transistor can be connected in parallel to the n-channel transistor to form a complementary metal-oxide-semiconductor (CMOS) bus switch.
FIG. 2
shows p-channel transistor
12
connected in parallel with n-channel transistor
10
to form a CMOS bus switch. An enable signal is applied to the gate of n-channel transistor
10
. An inverter generates the inverse of the enable signal, which is applied to the gate of p-channel transistor
12
. Thus both transistors
10
,
12
are enabled or disabled at the same time.
A CMOS bus switch does not develop a voltage drop across the source and drain terminals, even when reduced power supplies are used. For high signals when n-channel transistor
10
becomes saturated, p-channel transistor
12
is still in the linear region of operation and thus passes a full 3-volt signal across its channel without the threshold-voltage drop experienced by an n-channel transistor.
FIG. 3
shows the on-resistance across NMOS and CMOS bus switches. On-resistance
16
from source to drain through the transistor's channel varies with the drain voltage for the NMOS bus switch. On-resistance
16
rises sharply as the saturation voltage is reached. In contrast, on-resistance
14
for the CMOS bus switch is relatively constant for all drain voltages, since the p-channel transistor becomes more conductive to compensate for the n-channel transistor becoming less conductive as the drain voltage is increased.
Live Insertion
FIG. 4
Modern networking equipment is often reconfigured. It is desirable to add network boards or cards to a backplane bus without powering down the bus and thus shutting down the network. This is known as hot insertion or live insertion.
FIGS. 4A-4C
illustrate live insertion.
In
FIG. 4A
, hot bus
20
is a network bus such as a backplane bus in a chassis or equipment rack. Hot bus
20
is powered up and active, having signals in high and low states. These signals may be changing rapidly during the insertion sequence.
A network card is to be inserted into a slot in the chassis, and a connector on the card is to be plugged into a connector on the chassis connected to hot bus
20
. The network card includes interface circuitry
22
and bus switch
18
. Since no power has yet been applied to the network card, both interface circuitry
22
and bus switch
18
are powered down, with their power supply V
DD
floating or grounded at 0 volts.
In
FIG. 4B
, the network card has been inserted into the chassis, and the connectors plugged together. Bus switch
18
is electrically connected to hot bus
20
. Bus switch
18
must electrically isolate hot bus
20
from interface circuitry
22
, even though power has not yet been applied to interface circuitry
22
or even to bus switch
18
.
In
FIG. 4C
, the inserted network card is powered up. The card's internal power supply V
DD
reaches 3 volts in a few milliseconds after plugging the card into the connector. However, during these few milliseconds, hot bus
20
must be isolated from interface circuitry
22
by bus switch
18
; otherwise the signals on hot bus
20
can be disturbed. Data on hot bus
20
can be lost since high data rates use only a few microseconds or nanoseconds for each data transfer.
Once powered up, interface circuitry
22
can connect to hot bus
20
by enabling switch
18
. An enable signal is generated by control logic in interface circuitry
22
or other logic on the inserted network card.
NMOS bus switches are ideal for live-insertion applications, since n-channel transistors do not conduct when their gates are grounded. The drains of n-channel transistors can be directly connected to the hot bus since the p-type substrates are also grounded, preventing the forward-biasing of any p-n junctions.
CMOS bus switches pose several problems for live insertion since p-channel transistors conduct current when their gates are grounded.
FIG. 5
shows how a p-channel transistor in a CMOS bus switch can latch up during live insertion. During live insertion, as shown in
FIG. 4B
, the hot bus has some high signals while the interface circuitry and the bus switch are powered down. Most or all signals in powered-down circuitry is at zero volts, even when floating.
Thus the hot-bus side of the CMOS bus switch can be high, at 3 volts, while the other side is powered-down at ground. While n-channel transistor
10
does not conduct since its gate is also at ground, p-channel transistor
12
can conduct current from hot bus
20
when its gate is at ground. Even as the bus switch is powered up, p-channel transistor
12
can continue conducting current from the hot bus until its gate reaches 2 or 3 volts.
An even more serious problem is that the drain of p-channel transistor
12
can initiate latch up. The p+ drain is connected to the hot bus, which may be high at 3 volts. The N-well under p-channel transistor
12
is grounded when powered down. The P+ drain-to-N-well diffusions form a p-n diode that is forward biased. Since the N-well is rather large with many capacitances, it may be slow to power up to 3 volts. Thus latch up can occur during power up of CMOS bus switches. Even if latch up is not fully developed during power up, the forward biased p-n junction can discharge the hot bus. Additionally, when power is disconnected, these diodes pull the bus to one diode drop above ground, interfering with the normal operation of the hot bus.
The hot bus can be disturbed, causing data loss, when current is connected through p-channel transistor
12
, or through the forward-biased p-n junction.

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