Electronic digital logic circuitry – Reliability
Reexamination Certificate
1999-10-27
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S013000, C326S027000, C257S369000, C257S371000, C365S072000, C365S176000, C365S181000
Reexamination Certificate
active
06278287
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to both analog and digital CMOS circuits and provides a design architecture, which can be utilized to improve the single event upset hardness of any CMOS circuit design.
BACKGROUND OF THE INVENTION
Erroneous signals can be produced in electronic circuits whenever high energy ionizing radiation, such as cosmic rays, impinge on a region of the circuit having a high electric field, such as the drain-well boundary of an MOS transistor when it is in its high impedance, or “off” state. This phenomenon, known as single event upset or SEU, is a serious problem for electronics in the high radiation environment of space. More recently, as a result of increasing circuit density, SEU has also become a problem for avionics and certain special land based applications.
Traditional circuit design methods for dealing with SEU have primarily focused on static digital logic architectures. In these architectures, SEU induced errors occur by a process of circuit interactions in which an SEU transient error changes a stored static logic “bit” to its opposite, and hence wrong, state. Methods shown in U.S. patents for mitigating SEU in static logic include circuit redundancy (U.S. Pat. Nos. 5,307,142, 5,111,429), resistive attenuation (U.S. Pat. Nos. 4,914,629, 5,525,923), delayed circuit response (U.S. Pat. Nos. 5,504,703, 4,785,200) capacitive dissipation, and high current rapid recovery. A common feature of all these methods is that they serve to mitigate static errors but do not prevent transient errors from entering the logic stream but “correct” these errors after they have occurred. In addition, most of these techniques only apply to the storage elements of the circuit (i.e., registers and memory) and do not address the transient errors being generated within the combinational logic elements (inverters and gates, or gates, etc.).
This invention can be applied to every CMOS circuit logic function (i.e., inverter, and/or mux, memory, etc.) to produce an SEU hardened equivalent circuit. It is particularly applicable to a new type of logic architecture known as “dynamic logic” which is being developed as a way to improve the speed, power, and density of digital integrated circuits. Dynamic logic achieves these through heavy use of combinational elements and few if any static storage elements. Dynamic logic operates by rapid processing and propagation of dynamically held logic states of very short duration. The duration of these states is on the same scale as the erroneous transients signals of SEU's. The traditional methods of SEU mitigation listed in the previous paragraph do not prevent transient errors from entering the logic stream. While these methods are suitable for static logic, they are not effective for dynamic logic architectures because they would defeat the power, speed, and/or density advantages of dynamic logic. Because of this, no serious attempts have been made to SEU “harden” dynamic logic and this architecture has largely been relegated to non-radiation environments. What is needed for dynamic logic is a mitigation method that prevents the SEU transients from reaching the logic stream of the circuit. The invention described herein accomplishes this with a novel MOS transistor circuit structure that isolates the source of the transient from the logic node.
This invention also has applications in analog circuits. In these circuits this technique may be applied to alter the short duration, large voltage pulse of a typical SEU signal into a longer duration, lower voltage disturbance that is more acceptable to circuit operation.
OBJECTS OF THE INVENTION
It is an object of this invention to provide a transistor circuit structure that can be used to SEU harden any type of CMOS circuit.
BRIEF SUMMARY OF THE INVENTION
This invention places an SEU immune transistor(s) between the SEU sensitive transistors of a circuit and the circuit node of those sensitive transistors are driving. It then biases the immune transistor(s) such that it will block erroneous signals when the sensitive transistors are in their SEU sensitive “off” state and pass signals whenever the sensitive transistors are in their non-SEU sensitive “on” state. Dissipation of the SEU signal is achieved with either a resistor or a second SEU immune transistor having a current drive capability that is low, so as to spread the SEU signal out over time and thus reduce the magnitude of its voltage change to an acceptable, non-disruptive level.
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Gardner Conrad O.
Tan Vibol
The Boeing Company
Tokar Michael
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