Isolated vertical PNP transistor without required buried layer

Details Isolated vertical PNP transistor without required buried layer Isolated vertical PNP transistor without required buried layer

1997-06-05

1998-11-17

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

438370, 438375, 438377, H01L 21331

Patent

active

058375902

ABSTRACT:
A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m. Although the transistor is vertically constructed, base and collector contacts (60 and 42-43) may be provided at a surface of the surface layer (12) opposite the substrate (11). A contact (62) may also be provided for the isolation layer (14) at the surface.

REFERENCES:
patent: 3391035 (1968-07-01), Mackintosh
patent: 3596115 (1971-07-01), Conzelmann
patent: 3698077 (1972-10-01), Dahlberg
patent: 4239588 (1980-12-01), Morishita et al.
patent: 4357622 (1982-11-01), Magdo et al.
patent: 5011784 (1991-04-01), Ratnakumar
patent: 5192992 (1993-03-01), Kim et al.
patent: 5208171 (1993-05-01), Ohmi
Analysis and Design of Analog Integrated Circuits, (Third Ed.) by Gray and Meyer, John Wiley & Sons, Inc. pp. 148-149 (1993).
S. Wolf & R.N. Tauber, "Silicon Processing for the VLSI ERA" vol. I, 1986 pp. 242-245, 296-299.

Affiliated with

Also associated with

Rating

Isolated vertical PNP transistor without required buried layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolated vertical PNP transistor without required buried layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolated vertical PNP transistor without required buried layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-883952