Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-09-02
2000-08-15
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438639, 438672, 438675, 438696, H01L 213205
Patent
active
061036129
ABSTRACT:
A method for the manufacture of isolated interconnect studs and the structure so produced is provided. The method includes: providing a semiconductor device including a first semiconductor structure having an upper surface and a second semiconductor structure having an upper surface, the first semiconductor structure having a sidewall and the second semiconductor structure having a sidewall, the sidewalls of the semiconductor structures defining a trench therebetween; forming a conformal layer of a spacer material on the first semiconductor structure and the second semiconductor structure including the respective sidewalls thereof; etching the layer of spacer material to remove the layer of spacer material from the upper surfaces of the semiconductor structures and to cause the layer of spacer material to become recessed along the sidewalls of the first semiconductor structure and the second semiconductor structure; forming a layer of a conductive material in the trench; and etching the layer of conductive material to form a stud of the conductive material in the trench so that the stud is coplanar with or recessed below the respective surfaces of the semiconductor structures to electrically isolate the stud from areas of electrical activity on the semiconductor device.
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Dickerson David L.
Howard Bradley J.
Booth Richard
Micro)n Technology, Inc.
Zarneke David A.
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