Isolated anti-fuse structure and method for fabricating same

Details Isolated anti-fuse structure and method for fabricating same Isolated anti-fuse structure and method for fabricating same

1997-05-29

2000-10-31

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257 50, H01L 2900

Patent

active

061406929

ABSTRACT:
An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

REFERENCES:
patent: 4072975 (1978-02-01), Ishitani
patent: 4569121 (1986-02-01), Lim et al.
patent: 5648678 (1997-07-01), Begley et al.
Microelectronic Processing, W. Scot Ruska, pp. 311-317, 1987.

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