Isochronous data transfer control method including packet...

Details Isochronous data transfer control method including packet... Isochronous data transfer control method including packet...

2006-05-30

2006-05-30

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S022000, C710S024000, C710S030000, C369S060010

Reexamination Certificate

active

07054959

ABSTRACT:
A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1(IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1side.

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