Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-04-03
2002-09-17
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S664000, C438S683000
Reexamination Certificate
active
06451679
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method whereby a selective salicide process forms titanium salicide on exposed MOSFET CMOS devices using ion implantation for effective ion mixing between a two-step titanium deposition process.
(2) Description of Related Art
An important challenge in MOSFET CMOS technology is to form low resistance silicides on lightly doped source/drains (LDD), without affecting device electrical performance.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,940,726 entitled “Method for Forming an Electrical Constant for Embedded Memory” granted Aug. 17, 1999 to Yu describes a method for forming an MOSFET memory device that utilizes a titanium silicide layer in a contact opening. Electrical contact within a deep contact opening is described. A contact opening is etched through a dielectric layer to a semiconductor substrate. Good electrical contact is reported to be made, wherein the contact opening has an aspect ratio greater than one, and wherein, contaminants are found on the surface of the semiconductor substrate, at the bottom of the contact opening. A titanium layer is deposited overlying the dielectric layer and within the contact opening. Silicon ions are implanted into the substrate at a vertical implant wherein the peak implant dose is targeted for the interface between the titanium layer and the semiconductor substrate within the contact opening. Thereafter, the substrate is annealed, whereby the titanium layer is transformed into titanium silicide, and whereby, the contaminants are broken up. Thereafter, a metal layer is deposited within the contact opening, to complete the electrical contact.
U.S. Pat. No. 5,899,741 entitled “Method of Manufacturing Low Resistance and Low Junction Leakage Contact” granted May 4, 1999 to Tseng et al. describes a process wherein an amorphous silicon layer is deposited and ion implanted before a titanium deposition. The method teaches the deposition of an amorphous silicon glue layer in the formation of a contact. An insulating layer is deposited overlying semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed, whereby, the titanium layer reacts with the amorphous silicon layer, and the silicon semiconductor substrate, to form titanium silicide. The metal layer is etched back or patterned to complete metallization in the fabrication of an integrated circuit device.
U.S. Pat. No. 5,801,086 entitled “Process for Formation of Contact Conductive Layer in a Semiconductor Device” granted Sep. 1, 1998 to Lee describes a method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and can be selected from high melting point metals including: Co, Ti, Ta, Ni, Mo, and Hf. The ions used include H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions spread on/in the grain boundaries. Further, silicidation heat treatments are carried out so that the silicide forms on the portion where the metal and the silicon substrate contact together.
U.S. Pat. No. 5,851,912 entitled “Modified Tungsten-Plug Contact Process” granted Dec. 22, 1998 to Liaw et al. teaches a method for the fabrication of an ohmic, low resistance contact to heavily doped silicon, using a chemical vapor deposition (CVD) of a tungsten-plug provided with a Ti/TiN barrier metallurgy. Contact holes are patterned in a borophosphosilicatc glass insulator and the exposed silicon substrate contacts are implanted. Instead of activating the implant with a rapid-thermal-anneal (RTA), at this point, the Ti/TiN barrier metallurgy is applied first, then followed by an anneal. By using the Ti/TiN metallurgy to support the glass, higher annealing temperatures are permitted.
U.S. No. 5,780,349 entitled “Self-Aligned MOSFET Gate/Source/Drain Salicide Formation” granted Jul. 14, 1998 to Naem describes the formation of an MOSFET device structure that includes planarized trench isolation field oxide regions in a silicon substrate. A layer of cobalt is deposited on a polysilicon gate and raised source/drain polysilicon regions. The cobalt layer is then implanted with heavy ions to mix the cobalt and silicon at the cobalt/poly interface. A thin titanium nitride film is then formed on the cobalt layer to protect the cobalt film from nitrogen diffusion during rapid thermal annealing (RTA). A second anneal step is then performed to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming an integrated circuit in which a selective salicide process forms titanium salicide on exposed MOSFET CMOS devices, using ion implantation for effective ion mixing between a two-step titanium deposition process.
A high energy process utilizing ion implantation of Si through a Ti layer to the Ti/Si interface with ion mixing is very useful for reducing the sheet resistance of Ti salicide on narrow lines. However, high energy implantation induces many defects, i.e., Si interstitials, which contribute to transient enhanced diffusion (TED) and degradation of device performance. Therefore, in the present invention, the Ti layer thickness is reduced, so that, the implant energy can be reduced, and thus, this present process avoids any negative effects on device performance. Another deposition of Ti is performed, to maintain adequate film thickness and adequate cross-sectional area for low resistance of the salicide.
A more specific object of the present invention is to provide an improved method of forming an integrated circuit in which a salicide layer is formed on sub-0.25 micron, high performance MOSFET CMOS devices with lightly doped drains (LDD) and polysilicon narrow gate stacks. Prior to the special selective titanium deposition process for titanium salicide formation, openings are formed on the top of polysilicon gates and source/drain regions. In subsequent processing steps, titanium salicide is selectively formed on both the N-channel and P-channel FET's, on the exposed silicon SID regions and exposed polysilicon regions.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a salicide layer on a semiconductor substrate, wherein, the main embodiments of the present invention are: ion mixing between a two-step Ti deposition process for titanium salicide, TiSi
2
, formation. More specifically, the first key process step, in the present invention, is the deposition of a thin titanium layer on exposed silicon regions, in contact with exposed polysilicon gates and source/drain regions. The second key process step is an ion implantation of silicon through the titanium layer, peaking the maximum silicon dose at just below the Ti/Si interface. Note, key to this process step is that the ion implantation energy is low.
The third key p
Hu Chu-Wei
Shiue Ruey-Yun
Weng Jine-Wen
Ackerman Stephen B.
Everhart Caridad
Lee Calvin
Saile George O.
Taiwan Semiconductor Manufacturing Company
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