Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-01-08
1999-07-13
Chaudhuri, Olik
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438659, 257340, H01L 21283
Patent
active
059240016
ABSTRACT:
A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. Silicon ions are implanted into the silicide layer. A hard mask layer is deposited over the silicide layer. Because of the presence of the silicon ions in the silicide layer, silicon atoms from the polysilicon layer do not diffuse into the silicide layer causing voids to form in the polysilicon layer. Therefore, the formation of silicon pits in the semiconductor substrate is prevented. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.
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Chen Bou Fun
Szuma Liang
Wang Chien-Jiun
Wang Jih-Wha
Yang Chie-Ming
Ackerman Stephen B.
Chaudhuri Olik
Coleman William David
Pike Rosemary L.S.
Saile George O.
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