Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Implanting to form insulator
Reexamination Certificate
2002-07-05
2004-10-19
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Implanting to form insulator
C438S589000, C438S440000
Reexamination Certificate
active
06806163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming topographic features within microelectronic substrates. More particularly, the present invention relates to methods for forming, with rounded corners, topographic features within microelectronic substrates.
2. Description of the Related Art
Common in the art of semiconductor fabrication when fabricating semiconductor integrated circuits within semiconductor substrates is the use of isolation regions formed within isolation trenches which in turn define active regions of the semiconductor substrates. Isolation regions formed within isolation trenches generally provide an effective means for electrically isolating various semiconductor devices formed within the active regions of the semiconductor substrates.
While isolation regions formed within isolation trenches are thus clearly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, isolation regions formed within isolation trenches are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, as microelectronic integration levels have increased and microelectronic device dimensions have decreased, it has become increasingly difficult in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication, to fabricate isolation trenches and isolation regions with limited detrimental impact to microelectronic devices, and in particular semiconductor devices, formed within active regions adjacent the isolation trenches and isolation regions.
It is thus towards the goal of forming within semiconductor substrates isolation trenches and isolation regions with limited detrimental impact to semiconductor devices formed within active regions adjacent the isolation trenches and isolation regions that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming, with desirable properties, isolation regions within isolation trenches within microelectronic substrates.
Included among the methods, but not limited among the methods, are methods disclosed within Fuller et al., in U.S. Pat. No. 6,174,787 (an ion implantation method for forming, with round corners, isolation trenches within semiconductor substrates), the disclosure of which is incorporated herein fully by reference.
Desirable in the art of microelectronic fabrication are additional methods for forming within microelectronic substrates isolation trenches and isolation regions with limited detrimental impact to microelectronic devices formed within active regions adjacent the isolation trenches and isolation regions.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming an isolation region within an isolation trench within a microelectronic substrate.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the isolation region and the isolation trench are formed with limited detrimental impact to a microelectronic device formed within an active region adjacent the isolation trench and the isolation region.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic fabrication.
To practice the method of the present invention, there is first provided a microelectronic substrate having formed therein a topographic feature defined by a mask layer formed over the microelectronic substrate. There is then laterally etched the mask layer to form a laterally etched mask layer which uncovers a corner of the topographic feature. There is then ion implanted into the corner of the topographic feature, while employing the laterally etched mask layer as an ion implantation mask layer, a dose of an ion selected from the group consisting of silicon containing ions, germanium containing ions, arsenic containing ions, phosphorus containing ions and boron containing ions. Finally, there is then thermally oxidized the microelectronic substrate to form adjoining the topographic feature a thermal oxide layer.
Within the invention, the dose of the ion is of a mass, density and energy such that when thermally oxidizing the microelectronic substrate the corner of the topographic feature is rounded when forming the thermal oxide layer.
The invention provides particular value within the context of forming, with a rounded corner, an isolation trench within a semiconductor substrate.
The present invention provides a method for forming an isolation region within an isolation trench within a microelectronic substrate, wherein the isolation region and the isolation trench are formed with limited detrimental impact to a microelectronic device formed within an active region adjacent the isolation trench and the isolation region.
The present invention realizes the foregoing object by ion implanting a corner of a topographic feature within a microelectronic substrate, such as a corner of a trench within a semiconductor substrate, with a dose of an ion selected from the group consisting of silicon containing ions, germanium containing ions, arsenic containing ions, phosphorus containing ions and boron containing ions, such that when thermally oxidizing the microelectronic substrate to form a thermal oxide layer adjoining the topographic feature, such as a thermal oxide liner layer within the trench, the corner of the topographic feature is rounded. Within the present invention, the corner of the topographic feature is ion implanted while employing a laterally etched mask layer formed from a mask layer originally registered with respect to the topographic feature.
REFERENCES:
patent: 5223445 (1993-06-01), Fuse
patent: 5915195 (1999-06-01), Fulford, Jr. et al.
patent: 6022796 (2000-02-01), Berry et al.
patent: 6174787 (2001-01-01), Fuller et al.
patent: 6265317 (2001-07-01), Chiu et al.
Stanley Wolf et al. “Silicon Processing for the VLSI era vol. 1: Process Technology” Lattice Press p 283.
Sun Hsueh-Li
Wu Jie-Shing
Nguyen Van Thu
Smith Bradley
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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