IO completion architecture for user-mode networking

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S019000, C710S020000, C710S033000, C710S051000, C709S219000

Reexamination Certificate

active

06988268

ABSTRACT:
A new method and framework for implementing network protocol processing utilizing a combination of application threads and a dedicated thread to process IO completions in a completion queue that automatically detects and adjusts thread priorities to alleviate manual intervention. According to the present invention, as data transfer operations are completed by the network interface, completion information identifying the data transfer operations is posted on the completion queue. The completion information is read and processed by a combination of application and dedicated threads running in the system. A method monitors performance of the system to detect whether poor processor utilization or excessive context switches occurs, in which case a different thread is used to process the completion information. In order to context switch to a different thread, the priority level of the dedicated thread is set to a HIGH level to utilize the dedicated thread or the priority level of the dedicated thread is set a LOW level to utilize an application thread.

REFERENCES:
patent: 5758184 (1998-05-01), Lucovsky et al.
patent: 5778221 (1998-07-01), Temple
patent: 5835763 (1998-11-01), Klein
patent: 6065089 (2000-05-01), Hickerson et al.
patent: 6105122 (2000-08-01), Muller et al.
patent: 6219690 (2001-04-01), Slingwine et al.
patent: 6223207 (2001-04-01), Lucovsky et al.
patent: 6571282 (2003-05-01), Bowman-Amuah
patent: 6611882 (2003-08-01), Schmisseur
patent: 6658469 (2003-12-01), Massa et al.
patent: 6675238 (2004-01-01), Coffman et al.
patent: 6754738 (2004-06-01), Brice et al.
patent: 2001/0051972 (2001-12-01), Eydelman et al.
patent: 2002/0007420 (2002-01-01), Eydelman et al.
patent: 2003/0067913 (2003-04-01), Georgiou et al.
patent: 2003/0140179 (2003-07-01), Wilt et al.
“The process-Flow Model: Examining I/O Performance from the System's Point of view”, Gregory R. Graner, Yale N. Patt, ACM 1993.
Modeling and optimizing I/O throughput of multiple disks on a bus, Rakesh barve, et al., ACM 1999.
Apparna et al., “Monitoring Ethernet Network Activity with NDIS Drivers—Whitepaper,”California Software Laboratories Techguide,pp. 1-16 (Jan. 1999) printed at http://www.cswl.com/whiteppr/white/ethernet.html.
Bsy, “Virtual Memory,”CSE 30—Lecture 17,UC San Diego, pp. 1-2 (Nov. 1996) printed at http://www.cs.ucsd.edu/classes/fa96/cse30/lec17/.
Druschel et al., “Lazy Receiver Processing (LRP): A Network Subsystem Architecture for Server Systems,”Proceedings of the 2ndSymposium on Operating Systems Design and Implementation(ODSI), pp. 261-275 (Oct. 1996).
Haines et al., “On the Design of Chant: A Talking Threads Package,”Proceedings of Supercomputing '94,pp. 350-359 (1994).
Madukkarumukumana et al., “Harnessing User-Level Networking Architectures for Distributed Object Computing Over High-Speed Networks,”USENIX Papers,pp. 1-14 (1998) printed at http://www.usenix.org/publications/library/proceedings/usenix-nt98/full—papers/mad . . . /madukkarum.htm.
Microsoft Corporation, “System Area Networks,”Microsoft Windows Platform Development,1 pg (2001) printed at http://www.microsoft.com/hwdev/tech
etwork/san/default.asp.
Microsoft Corporation, “Winsock Direct and Protocol Offload on SANs,”Windows Platform Design Notes,pp. 1-8 (2001).
Mogul et al, “Eliminating Receive Livelock in an Interrupt-driven Kernel,”WRL Research Report 95/8,Digital Western Research Laboratory, pp. 1-46 (1995).
PCAUSA, “Windows Networking Architecture,”RAW Ether for Windows,pp. 1-4 (2001) printed at www.rawether.net/product/tour01.htm.
Pinkerton, Jim, “Winsock Direct: The Value of System Area Networks,” pp. 1-15 (2001) printed at http://microsoft.com/TechNet/itsolutions
etwork/evaluate/technol/wsockdir.asp?frame-true.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

IO completion architecture for user-mode networking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IO completion architecture for user-mode networking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IO completion architecture for user-mode networking will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3524629

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.