Inverting logic buffer BICMOS switching circuit using an enablin

Details Inverting logic buffer BICMOS switching circuit using an enablin Inverting logic buffer BICMOS switching circuit using an enablin

1985-02-22

1987-07-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, 307570, 307270, H03K 1704

Patent

active

046789430

ABSTRACT:
A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.

REFERENCES:
patent: 3541353 (1970-11-01), Seelbach et al.
patent: 4280065 (1981-07-01), Minato et al.
patent: 4322640 (1982-03-01), Fukushima et al.
patent: 4488067 (1984-12-01), Kraft et al.
patent: 4542310 (1985-09-01), Ellis et al.
Griffin et al, "Low Power Tri-State Driver Circuit", IBM Tech. Discl. Bull., vol. 24, No. 5, pp. 2556-2557, 10/1981.
Kraft et al, "Tristate Driver Utilizing Bipolar-Complementary MOS Technology", IBM-TDB; vol. 16, No. 8, pp. 2677-2678; 1/1974.
Lin et al, "Complementary MOS-Bipolar Transistor Structure"; IEEE/Trans. on E/D; vol. ED-16, No. 11, pp. 945-951; 11/1969.

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