Inverting flip-flop for use in field programmable gate arrays

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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Details

C326S038000, C326S039000

Reexamination Certificate

active

07932745

ABSTRACT:
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

REFERENCES:
patent: 4638183 (1987-01-01), Rickard et al.
patent: 5495182 (1996-02-01), Hardy
patent: 5502403 (1996-03-01), Liu et al.
patent: 5583451 (1996-12-01), Sharpe-Geisler
patent: 5621338 (1997-04-01), Liu et al.
patent: 5635856 (1997-06-01), Raza et al.
patent: 5796624 (1998-08-01), Sridhar et al.
patent: 6121797 (2000-09-01), Song et al.
patent: RE37577 (2002-03-01), Liu et al.
patent: 6466049 (2002-10-01), Diba et al.
patent: 6477695 (2002-11-01), Gandhi
patent: 6785875 (2004-08-01), Beerel et al.
patent: 6993737 (2006-01-01), Anderson et al.
patent: 7816946 (2010-10-01), Hecht et al.
patent: 2007/0007996 (2007-01-01), Ranganathan
patent: 2007/0136706 (2007-06-01), Hwange et al.
patent: 2010/0192117 (2010-07-01), Zhu et al.
Co-pending U.S. Appl. No. 11/859,678, filed Sep. 21, 2007 entitled Architecture and Method for Compensating for Disparate Signal Rise and Fall Times by Using Polarity Selection to Improve Timing and Power in an Integrated Circuit.
Office Action mailed Nov. 17, 2009 in co-pending U.S. Appl. No. 11/859,678, filed Sep. 21, 2007.
Anderson, J. H. et al., “Active Leakage Power Optimization for FPGAs”, Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Array, 2004, pp. 33-41, Monterey, California, USA.
Zhu, Kai, “Post-Route LUT Output Polarity Selection for Timing Optimization”, Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Feb. 18-20, 2007, held in Monterey, California, USA, pp. 89-96, ACM Press, 2007.

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