Inverter made of complementary p and n channel transistors...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S151000, C438S153000, C157S001420, C157S001420

Reexamination Certificate

active

06713329

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the fabrication of large area electronic products, and more specifically to the fabrication of complimentary metal-oxide semiconductor (CMOS) circuits for add-on electronics for application-specific integrated circuits (ASICs), at low temperatures by directly depositing microcrystalline thin-film silicon (&mgr;C-Si).
2. Related Art
It is known how to make CMOS circuits at temperatures in excess of 600° C., which is the lowest temperature at which polycrystalline films can be made by thermal crystallization. These films are then processed to CMOS circuits.
An ultralow-temperature, large-area silicon technology that could furnish a tool kit of standard devices, including transistors, rectifying diodes and photodiodes is of great interest for applications in macroelectronics, and in add-on electronics for application-specific integrated circuits. The latter application of the process temperature expands the applicability of macroelectronics. A widely usable ultralow-temperature technology needs p channel and n channel field-effect transistors (FETs), which are the building blocks for complementary digital circuits n channel FETs made of directly deposited microcrystalline silicon (&mgr;c-Si) indeed have been reported by: T. Nagahara, K. Fuiimoto. N. Kohno. Y. Kashiwapi and H. Kakinoki, Jpn. J. Appl. Phys. 31, 4555 (1992); J. Woo, H. Lim and J. Jane, Appl. Phys. Lett. 65, 1644 (1994); H. Meiling, A. M. Brockhoff J. K. Rath and R.E.I. Schropr), Mat. Res. Soc. Symp. Proc. 508, 31 (1998); and Y. Chen and S. Wagner, Electrochem. Soc. Proc. 98-22, 221 (1998). The fabrication of solar cells of &mgr;c-Si suggests that useful hole mobilities can be obtained in &mgr;c-Si. However, no p channel thin film transistors (TFTs):have been made of hydrogenated amorphous silicon (a-Si:H), which is an efficient solar cell material.
What would be desirable, but has not heretofore been developed, is a method of fabricating macroelectronic devices and ASICs at low temperatures by directly depositing &mgr;c-Si and integrating a p channel TFT with an n channel TFT to form an inverter.
OBJECTS AND SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a method of making large area electronic devices at low temperatures.
It is another object of the present invention to provide a method of making CMOs circuits at low temperatures.
It is another object of the present invention to provide a method of making TFTs by directly depositing &mgr;c-Si.
It is an additional object of the present invention to provide a method of integrating p channel and n channel TFTs to form an inverter.
It is even a further object of the present invention to provide a method for making p channel and n channel transistors from the same film of &mgr;c-Si.
It is even an additional object of the present invention to provide a TFT wherein the p and n channels share a single &mgr;c-Si layer.
A p channel TFT is made of directly deposited microcrystalline silicon (&mgr;c-Si). The p TFT is integrated with its n channel counterpart on a single &mgr;c-Si film, to form a complementary metal-silicon oxide-silicon (CMOS) inverter of deposited &mgr;c-Si. The &mgr;c-Si channel material can be grown at low temperatures by plasma-enhanced chemical vapor deposition in a process similar to the deposition of hydrogenated amorphous silicon. Either the p
+
or n
+
layers can be grown and patterned, and then the other can be deposited and patterned. The p and n channels share the same &mgr;c-Si layer.


REFERENCES:
patent: 4889609 (1989-12-01), Cannella
patent: 4980303 (1990-12-01), Yamauchi
patent: 5223449 (1993-06-01), Morris et al.
patent: 5576229 (1996-11-01), Murata et al.
patent: 5766989 (1998-06-01), Maegawa et al.
patent: 5808316 (1998-09-01), Matsuda et al.
patent: 5834071 (1998-11-01), Lin
patent: 5899709 (1999-05-01), Yamazaki et al.
patent: 5923050 (1999-07-01), Jang et al.
patent: 5946561 (1999-08-01), Yamazaki et al.
patent: 5959312 (1999-09-01), Tsai et al.
patent: 5962896 (1999-10-01), Yabuta et al.
patent: 6037610 (2000-03-01), Zhang et al.
patent: 6100466 (2000-08-01), Nishimoto
Chen et al. “Effects of Grow Parameters on the Performance of uc-Si TFTs”, Electrochemical Society Proceedings, vol. 98-22, pp. 221-229 (1998).*
Chen et al. “TFTs of uc-Si deposided by PECVD”, Mat. Rec. Soc. Symp. Proc., 557:665-670, 1999.*
Chen, et al., “Effects of Growth Parameters on the Performance of uc-Si Thin Film Transistors Deposited Using SiF4,” Electrochemical Society Proceedings vol. 98-22, pp. 221-229 (1998).
Meiling, et al., “Transistors With a Profiled Active Layer Made by Hot-Wire CVD,” Mat. Res. Soc. Symp. Proc. vol. 507, pp. 31-36, (1998).
Nagahara, et al., “In-Situ Chemically Cleaning Poly-Si Growth at Low Temperature,” Jpn., J. Appl. Phys. vol. 31, pp. 4555-4558 (1992).
Woo, et al., “Polycrstalline Silicon Thin Film Transistors Deposited at Low Substrate Temperature by Remote Plasma Chemical Vapor Deposition Using SiF4/H2,” App. Phys. Lett. vol. 65, No. 13, pp. 1644-1646 (1994).
Chen, Yu et al., “Low Temperature Growth of Nanocrystal Silicon From SiF4+SiH4,” Mat. Res. Soc. Symp. Proc., 424:103-107, 1997.
Chen, Y. and Wagner, S., “Thin Film Transistors of Microcrystalline Silicon Deposited By Plasma Enhanced-CVD,” Mat. Res. Soc. Symp. Proc., 557:665-670, 1999.
Ma, E.Y. and Wagner, S., “Amorphous silicon transistors on ultrathin steel foil substrates,” Applied Physics Letters, 74(18):2661-2662, May 1999.
Meier, J. et al., “Complete microcrystalline p-i-n solar cell—Crystalline or amorphous cell behavior?,” Applied Physics Letters, 65(7):860-862, Aug. 1994.
Nakata, M., “Growth Processes of Silicon Thin Films in Various Structural Phases Manufactured from Silicon Tetrafluoride at Low Temperatures,” thesis, Tokyo Institute of Technology, Department of Electronic Chemistry, 1992.
Schneider, B. et al., Image Sensors in TFA (Thin Film on ASIC) Technology, Handbook of Computer Vision and Applications, vol. 1, pp. 237-270, Academic Press, 1999.
Yang, J. et al., “Triple-junction amorphous silicon alloy solar cell with 14.6% initial and 13.0% stable conversion efficiencies,” Applied Physics Letters, 70(22):2975-2977, Jun. 1997.

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