Inverter for high voltage full swing output

Details Inverter for high voltage full swing output Inverter for high voltage full swing output

2000-01-18

2001-07-17

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S119000, C326S068000, C326S086000

Reexamination Certificate

active

06262601

ABSTRACT:

This Application claims the benefit of Korean Patent Application No. 99-24160 filed on Jun. 25, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inverter for high voltage full swing output, and more particularly, to an inverter circuit which generates a full swing output in the range of zero volt (ground voltage) to a value of a high voltage source.
2. Discussion of the Related Art
As shown in
FIG. 1
, a high voltage inverter of related art includes a first super transistor SP and a second super transistor SN. The first super transistor SP consists of PMOS transistors P
1
and P
2
. The second super transistor SN consists of NMOS transistors N
1
and N
2
. The high voltage inverter is connected between a high voltage source HVDD and ground voltage GND (which is normally zero), and is operated by the high voltage source HVDD and a shield voltage source VSHLD (VSHLD=HVDD/2). The high voltage inverter received an input voltage HVin and generates an output voltage HVout.
More specifically, the inverter includes a PMOS P
2
connecting Vp (see
FIG. 1
) and HVDD to its drain terminal and bulk terminal, respectively. A PMOS P
3
connects Vp, HVout, and Vp to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N
2
connects GND, Vn, and GND to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N
3
connects Vn, HVout, and Vn to its source terminal, drain terminal, and bulk terminal, respectively. A PMOS P
1
connects HVin, a gate input of the PMOS P
2
, and the same gate input of the PMOS P
2
to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N
1
connects HVin, a gate input of the NMOS N
2
, and the same gate input of the NMOS N
2
to its source terminal, drain terminal and bulk terminal, wherein gates of the PMOS P
1
and P
3
, and NMOS N
3
and N
1
are connected to VSHLD. The structure formed of P
1
and P
2
with drain of the P
1
connected to gate input of the P
2
consists the first super transistor SP, while the structure formed of N
1
and N
2
with drain of the N
1
connected to gate input of the N
2
consists the second super transistor SN.
In the high voltage inverter described above, the shield voltage source VSHLD has to be supplied with a voltage of 3.3 V when a voltage of 6.6 V is applied to the high voltage source HVDD. Once a high voltage of 6.6 V is applied to HVin, the P
1
with its gate terminal connected to VSHLD becomes turned on while the N
1
becomes turned off. Thus, drain terminal of the P
1
is supplied with 6.6 V and source terminal of the N
1
is supplied with 3.3 V−Vtn (where Vtn is a threshold voltage of n-type MOS transistor), turning off the P
2
and P
3
and turning on the N
2
and N
3
. Therefore, 0 V is ouputted from the output terminal.
In this case, although a high voltage of 6.6 V is applied between the high voltage source and output terminal, each transistor operates within a low voltage level as the voltage of Vp is biased to 3.3+Vtp (where Vtp is a threshold voltage of p-type MOS transistor) by the shield voltage source VSHLD.
Otherwise, when 0 V is applied to the HVin, the P
1
with its gate terminal connected to VSHLD becomes turned off while the N
1
becomes turned on. Thus, a high voltage of 6.6 V is outputted from the output terminal by turning on the P
2
and P
3
but turning off the N
2
and N
3
. In addition, the voltage of the drain terminal of the P
1
and the voltage of Vn are biased to low voltage level by the shield voltage source VSHLD.
As a result, each of the transistors operates stably within the low voltage level due to the super transistors SP and SN and the shield voltage source VSHLD and enables a full-swing output between the high voltage source HVDD and ground GND.
However, the high voltage inverter of the related art as described above has the following disadvantages. The voltage level of the high voltage source (HVDD) of the inverter circuit can only be extended two times as high as the limit bias voltage of low voltage transistors used in the inverter circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an inverter for high voltage full swing output that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an inverter for high voltage full swing output which extends the voltage level of the high voltage source of the inverter circuit to a level which is higher than two times of the limit bias voltage of low voltage transistors.
Another object of the present invention is to provide an inverter for high voltage full swing output which generates a full swing output ranging from a voltage of a high voltage source to a ground voltage. The inverter of the present invention also operates stably with a low voltage applied to each transistor to prevent transistors from voltage breakdown and the like, so that the low voltage process set up by the related art can be used even though a high voltage supply is applied to the overall inverter circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an inverter for high voltage full swing output of the present invention generates an inverter output changing into full swing corresponding to supply voltage of a high voltage circuit wherein the supply voltage of a high voltage circuit is m of integer times higher than supply voltage of a low voltage circuit. The inverter of the present invention includes a switching circuit
10
consisting of 2 m transistors wherein the transistors are stacked one upon another, a feedback control circuit
30
supplying gates of the transistors of the switching circuit with bias voltage by reducing full swing inverter output voltage, and a shield voltage source generating shield voltage to control transmission of the bias voltage. The shield voltage source of the present invention includes a circuit having m PMOS transistors and m NMOS transistors which are connected in series, and wherein at least one high shield voltage HVshield and low shield voltage LVshield is generated from a joint interconnecting the transistors. The feedback control circuit of the present invention includes a serial circuit having m PMOS transistors and m NMOS transistors, and at least one passing transistor transmitting voltage of at least one transistor joint in the serial circuit to at least one gate of the stacked transistors of the switching circuit.
In another aspect of the present invention, an inverter for high voltage full swing output of the present invention generates an inverter output changing into full swing corresponding to supply voltage of a high voltage circuit wherein the supply voltage of a high voltage circuit is 3 times higher than supply voltage of a low voltage circuit. The inverter includes a switching circuit having a first to third PMOS transistors and a first to third NMOS transistors wherein the NMOS and PMOS transistors are stacked one another, a feedback control circuit supplying gates of the transistors of the switching circuit with bias voltage by reducing full swing inverter output voltage, and a shield voltage source generating shield voltage to control transmission of the bias voltage. The shield voltage source includes a serial circuit having a first to third PMOS transistors and a first to third NMOS transistors, wherein a high shield voltage is generated from a joint between the second and third PMOS transistors, and wherein a low shi

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