Inverter circuit

Electric power conversion systems – Current conversion – With condition responsive means to control the output...

Reexamination Certificate

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Details

C363S132000

Reexamination Certificate

active

06239998

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inverter circuit, and more particularly to an inverter circuit supplying polyphase power.
2. Discussion of the Background
FIG. 20
is a circuit diagram showing a configuration of a background-art inverter circuit
1
a
and connection of the circuit
1
a
and peripheral devices. Terminals P and N on both ends of a smoothing capacitor
70
are connected to a not-shown electronic power rectifier which can employ a diode bridge and the like and supplied with substantially-direct current power therefrom. The inverter circuit
1
a
converts the substantially-direct current power into three-phase electric power and supplies this power for a load
71
such as a motor M.
In the inverter circuit
1
a
, on each “L” side of U-phase, V-phase and W-phase, i.e., on a side connected to the terminal N provided are IGBTs (Insulated Gate Bipolar Transistor: hereinafter, simply referred to as “transistor”)
20
F,
21
F and
22
F each with a protective diode for producing a regenerative current. On each “H” side of the U-phase, the V-phase and the W-phase, i.e., on a side connected to the terminal P provided are IGBTs
23
F,
24
F and
25
F each with the protective diode. Their gates of the transistors
20
F,
21
F,
22
F,
23
F,
24
F and
25
F are connected to a controller
10
a
, and specifically their operations are controlled by a driving circuit
12
included in the controller
10
a
. Supplied with an overcurrent signal by an overcurrent protective circuit
11
, the driving circuit
12
controls the operations of the transistors so that no excess current may flow into the transistor in which an overcurrent possibly flows.
The possibility that an overcurrent flows in the transistor can be detected as follows. Emitters of the transistors
20
F,
21
F and
22
F on the “L” side are connected in common to one end of a resistor
30
. A voltage drop caused by a current flowing in the resistor
30
is given to one input end of a comparator
13
through a low-pass filter
45
consisting of a resistor
47
and a capacitor
46
. The other input end of the comparator
13
is connected to a power supply
14
for supplying a predetermined voltage Vref. An output of the comparator
13
is given to the overcurrent protective circuit
11
. Therefore, when a current large enough to cause a voltage drop higher than the voltage Vref flows in the resistor
13
, judging that an overcurrent flows in at least one of the transistors
20
F,
21
F and
22
F, the overcurrent protective circuit
11
applies the overcurrent signal to the driving circuit
12
. For example, the driving circuit
12
receives the overcurrent signal to turn off the transistors
20
F,
21
F and
22
F.
Thus, the technique to detect an overcurrent by a DC bus detection system is disclosed in e.g., Japanese Patent Application Laid Open Gazette No. 7-298481.
FIG. 21
is a circuit diagram showing a configuration of another background-art inverter circuit
1
b
and connection of the circuit
1
b
and peripheral devices. As compared with the inverter circuit
1
a
, the transistors
20
F,
21
F and
22
F on the “L” side are replaced by transistors
20
S,
21
S and
22
S each comprising a current detection terminal as well as the protective diode. The current detection terminals of the transistors
20
S,
21
S and
22
S are connected in common to the terminal N through resistors
30
u,
30
v
and
30
w,
respectively.
The inverter circuit
1
b
comprises a controller
10
b
. The controller
10
b
has control units
10
u,
10
v
and low corresponding to the respective phases, which control drivings of the transistors
20
S,
21
S and
22
S, respectively. For example, the control unit
10
u
comprises a comparator
13
u,
an overcurrent protective circuit
11
u
and a driving circuit
12
u.
One input end of the comparator
13
u
is connected to a power supply
14
u
for supplying the voltage Vref, and the other input end receives a voltage drop across the resistor
30
u
through a filter
45
u
having the same constitution as the filter
45
connected to the inverter
1
a.
The overcurrent protective circuit
11
u
gives overcurrent information to the driving circuit
12
u
on the basis of an output from the comparator
13
u.
For example, when the voltage drop across the resistor
30
u
is higher than the voltage Vref, judging that an overcurrent flows in the transistor
20
S, the driving circuit
12
u
given the overcurrent information from the overcurrent protective circuit
11
u
turns off the transistor
20
S. Similarly, the other control units
10
v
and
10
w
monitor voltage drops across the resistors
30
v
and
30
w
through filters
45
v
and
45
w
to control operations of the transistors
21
S and
22
S, respectively.
Thus, the technique to detect an overcurrent by a phase-current detection system using transistors having current detection terminals is disclosed in e.g., Japanese Patent Application Laid Open Gazette No. 9-219976.
The background-art technique to detect an overcurrent by the DC bus detection system has a problem that a loss across the resistor
30
becomes larger since a current flowing in a bus connected to the transistors
20
F,
21
F and
22
F causes the voltage drop across the transistor
30
. Further, as the resistor
30
, it is necessary to adopt a high-power resistor, so it disadvantageously costs high. Moreover, it is not easy to incorporate such a resistor in the inverter circuit
1
a
and it is necessary to separately provide the resistor outside the inverter circuit
1
a.
The background-art technique to detect an overcurrent by the phase-current detection system has a problem that it is impossible to reduce the size of the inverter circuit
1
b
since the respective current detection terminals of the transistors
20
S,
21
S and
22
S are connected to the controller
10
b
to increase the number of interconnection lines. Further, in order to transfer the voltage drops across the resistors
30
u,
30
v
and
30
w
to the control units
10
u,
10
v
and
10
w
while avoiding an effect of noise, it is necessary to provide the filters
45
u,
45
v
and
45
w
corresponding to the respective phases.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above problems by reducing the resistor for overcurrent detection and decreasing the number of filters.
The first aspect of an inverter circuit in accordance with the present invention is characterized in that the inverter connected to first and second terminals which are given a substantially-direct current and supplying polyphase power comprises: a plurality of switching elements on a first side, each including a first end connected to the first terminal, a second end and a regenerative current element provided between the first and second ends; a plurality of switching elements on a second side, each including a first end, a second end connected to the second terminal, a regenerative current element provided between the first and second ends thereof and a current detection terminal for detecting a current flowing therein; a resistive device developing a voltage drop by a sum of currents flowing in the second ends of the plurality of switching elements on the second side; and a driving circuit for controlling a driving operation on the plurality of switching elements on the second side on the basis of a comparison result between the voltage drop and a predetermined voltage, and the second ends of the plurality of switching elements on the first side and the first ends of the plurality of switching elements on the second side are connected to output the polyphase power.
The second aspect of the inverter circuit in accordance with the present invention is the first aspect of the inverter circuit, which is characterized in that the resistive device and the driving circuit are integrated.
The third aspect of the inverter circuit in accordance with the present invention is the first aspect of the inverter circuit, which is characterized in that the resistive devi

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