Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-11-21
2003-04-01
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S117000, C326S121000, C326S112000
Reexamination Certificate
active
06542007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inverter circuit with a small feedthrough current.
2. Related Background Art
An example of a conventional inverter circuit is shown in FIG.
2
. The conventional inverter circuit operates as described below.
An input voltage is supplied from an input terminal
205
. If the input voltage is VDD, no voltage is generated between the gate and source of a PMOS transistor
201
, so that the PMOS transistor
201
is placed in a cutoff state. On the other hand, the gate terminal and drain terminal of an NMOS transistor
202
are connected to each other, so that the impedance of the NMOS transistor
202
is small as viewed from an output terminal
206
. Accordingly, a voltage close to VSS or VSS is supplied to the output terminal
206
.
A potential difference occurs between the gate and source of the PMOS transistor
201
in accordance with the gradual reduction of the input voltage from VDD. When a voltage Vsg between the gate and source of the PMOS transistor
201
becomes larger than the absolute value of a threshold value voltage of the PMOS transistor
201
, the impedance between the drain and source of the PMOS transistor
201
starts to be decreased and the potential at the output terminal
206
starts to be increased.
When the input voltage reaches VSS, there occurs a potential difference corresponding to a power supply voltage (VDD−VSS) between the gate and source of the PMOS transistor
201
, so that the impedance between the drain and source of the PMOS transistor
201
assumes a minimum value. At this point in time, the potential at the output terminal
206
approaches VDD if the transistor sizes are determined so that the impedance between the drain and source of the PMOS transistor
201
is much smaller than the impedance between the drain and source of the NMOS transistor
202
.
In this manner, the circuit shown in
FIG. 2
operates as an inverter.
The conventional inverter circuit, however, has a problem in that a feedthrough current is increased as the input voltage approaches VSS, which increases current consumption. This is because the impedance between the drain and source of the PMOS transistor and the impedance between the drain and source of the NMOS transistor are both decreased when the input voltage becomes VSS.
SUMMARY OF THE INVENTION
To solve the above problem, in accordance with the present invention, a depletion type NMOS transistor is combined with a resistor so that a current limitation is imposed when a feedthrough current starts to flow. An inverter circuit constructed in this manner has a characteristic that a large feedthrough current does not flow even if an input voltage approaches VSS.
REFERENCES:
patent: 4578694 (1986-03-01), Ariizumi et al.
patent: 5834962 (1998-11-01), Okamoto
Chang Daniel
Seiko Instruments Inc.
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