Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-12-03
2001-12-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000
Reexamination Certificate
active
06326808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of circuitry for a programmable logic device (PLD) to limit the number of product term lines need to perform a Boolean operation.
2. Background
FIG. 1
shows an array structure for a typical prior art programmable array logic (PAL) device, a type of PLD. The PAL of
FIG. 1
has six inputs I
0-5
and four outputs O
0-3
. The PAL device further has an AND array
100
followed by an OR array
102
. An input such as I
0
to the PAL has a true output
104
and a complement output
106
forming rows connected to programmable interconnect cells
108
containing individual cells, such as
110
. A cell like cell
110
may be programmed to be connected or disconnected to an AND gate in the AND array
100
. Nonprogrammable interconnect points
120
connect the output of the AND gates
100
to the OR gates of the OR array
102
. Although points
120
are described as nonprogrammable, programmable cells may likewise be used. Additional programmable features may also be added, such an output macro cell
114
which is programmable to allow an output to be either registered or combinatorial.
A group of cells as shown at
112
may be connected to an AND gate with the output of the AND gate providing a product term. Although shown as an AND array
100
, in reality the AND array
100
has AND gates implemented using NOR gates with true and complement row connections to cells
108
reversed internally. An example of the PLD with circuitry similar to that shown and described with respect to
FIG. 1
is included in the MACH
4
PLDs manufactured by Lattice/Vantis Semiconductor Corporation of Sunnyvale, California.
FIG. 2
illustrates programming of a PAL device as shown in
FIG. 1
to perform the Boolean operation /a*b+a*/b+/b+a, where “/” indicates a Boolean NOT, “*” indicates a Boolean AND, and “+” indicates a Boolean OR operation. The PAL device of
FIG. 2
receives two inputs “a” and “b”. Inverting/Noninverting buffers
200
provides a and its inverse /a, while inverting
oninverting buffer
202
provides b and its inverse /b to be selectively connected to form four product terms
210
-
213
. For the first product term
210
, /a and b are connected to form the Boolean equation /a*b. For the second product term
211
, a and /b are connected to form the Boolean equation a*/b. For product term
212
only /b is connected, while for product term
213
only a is connected. Note that connected programmable interconnect cells are represented by a darkened circle symbol, while interconnect cells programmed to be unconnected are shown as a circle without darkening. The product terms
210
-
213
are provided to inputs of an OR gate
220
, so the output of OR gate
220
provides the desired Boolean operation /a*b+a*/b+/b+a.
SUMMARY OF THE INVENTION
In accordance with the present invention, a PLA circuit configuration is provided which uses less product term lines than a typical PLA to perform a similar operation. Such circuitry in accordance with the present invention enables the Boolean operation /a*b+a*/b+/b+a illustrated in
FIG. 2
to be performed with only three product terms, as opposed to the four product term lines used in the circuit of FIG.
2
.
In one embodiment of the present invention, an inverter is provided between the output of one product term line and the input of an OR gate. The inverter enables the one product term to provide an OR operation. This is because when two or more elements are ANDed in a product term, inverting the product term creates an OR operation with the elements inverted. With an OR operation provided using a single product term and inverter, less product term lines are needed when performing some operations.
For example, the elements /b and a are provided on separate product terms
212
and
213
to OR gate
220
to provide the operation /b+a in FIG.
2
. In accordance with the present invention, the terms b and /a can be ANDed using a single product term, and when the single product term line is inverted it will provide the operation /b+a without requiring use of a separate product term line and OR gate.
In accordance with another embodiment of the present invention, the output of the OR gate of the PAL device is provided to a first input of an exclusive OR (XOR) gate. A second input of the XOR gate as well as one input of the OR gate is driven by a product term line as provided through a buffer. The product term line voltage range is typically ±0.6 volts to enable rapid switching, but the input of the XOR gate is driven by a CMOS signal ranging from 0.0 to 5.0 volts. Buffering is, thus, provided between the product term line and XOR gate enabling translation between the different voltage ranges. An inverter can be provided between the buffer and XOR gate since the inverter is typically a CMOS device with a 0.0 to 5.0 volt input and output range.
In another embodiment in accordance with the present invention, the output of the OR gate of the PAL device is provided to the first input of a look up table (LUT), while a single product term line is provided to a second input of the LUT. The LUT can be programmably configured to perform a number of Boolean logic functions, such as an OR gate, an XOR gate, etc. An input to the LUT can further be programmed to be inverted, enabling a single product term input to the LUT to be used where two separate product terms might otherwise be required as described previously.
REFERENCES:
patent: 5789939 (1998-08-01), Agrawal et al.
patent: 6020759 (2000-02-01), Heile
patent: 6107822 (2000-08-01), Mendel et al.
Fisk Mathew
Patel Apurva
Sharpe-Geisler Bradley
Fliesler Dubb Meyer & Lovejoy LLP
Tokar Michael
Tran Anh Q.
Vantis Corporation
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