Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-10-16
2007-10-16
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S006000, C711S205000, C711S206000
Reexamination Certificate
active
10435919
ABSTRACT:
Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.
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Heller Lisa C.
Pfeffer Erwin F.
Plambeck Kenneth E.
Slegel Timothy J.
Campbell John E.
International Business Machines - Corporation
Namazi Mehdi
Padmanabhan Mano
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