Interweaved integrated circuit interconnects

Details Interweaved integrated circuit interconnects Interweaved integrated circuit interconnects

2001-02-14

2003-05-20

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06567966

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to the design and fabrication of integrated circuits (ICs) and, more particularly, is related to a system and method for interweaving interconnects on an integrated circuit to reduce interconnect-to-interconnect capacitance.
BACKGROUND OF THE INVENTION
The constant goals in the field of integrated circuit design and fabrication are to design and build faster, smaller, more powerful, and less expensive integrated circuits. As designers have built integrated circuits to meet these goals the designers have confronted, and for the most part overcome, a variety of obstacles. In general, overcoming one obstacle tends to give rise to a new obstacle. An obstacle that could safely be ignored in the past becomes critical limiting factors as a prior obstacle is overcome. Due to advances in the field, interconnect-to-interconnect capacitance, and associated interconnect delay, has ripened into a critical limitation in the design and fabrication of integrated circuits.
An integrated circuit is a group of functional blocks interconnected by conductors. The conductors are known as interconnects. In the past, while striving to build faster integrated circuits, interconnect delay could, for the most part, be ignored while attention was focused on overcoming other obstacles such as designing faster, smaller, and more powerful functional blocks. The functional blocks may be logic gates, transistors, state machines, algorithmic units, pads driving data off the chip and onto external devices, or any other functional integrated circuit unit. Functional blocks may also be defined as any device on an integrated circuit that is attached to an interconnect.
Interconnect delay is a function of the resistance and the capacitance associated with the interconnects. The resistance of the interconnects is proportional to the length and inversely proportional to the cross-sectional area of the interconnects. To meet the goal of designing and building more powerful integrated circuits, the number of functional blocks on integrated circuits has increased. The greater number of functional blocks must be interconnected in a smaller area to meet the goal of building smaller integrated circuits. This has lead to more complexity on the integrated circuit and greater interconnect routing congestion. To overcome these obstacles, interconnects have become thinner. As will become apparent below, thinner interconnects have drawbacks such as increased resistance. Designers have attempted to minimize the adverse effects of thinner interconnects by increasing the height of interconnects. In the midst of these changes interconnects have become longer in proportion to their height and width.
The increased resistance associated with thinner interconnects has also led to a need for repeaters. Repeaters are periodically spaced on the interconnect to boost the power of the signal carried by the interconnect. The increased power prevents the interconnect resistance from eroding the signal beyond the point of recovery prior to the time the signal arrives at the target functional block. The repeaters are often a buffer comprised of two inverters. The power boost the repeaters provide to the signal ultimately leads to faster signal speed. The interconnect can be envisioned as broken up into segments with each segment containing one repeater.
Unfortunately, the change in geometry of the interconnects has increased electrical interaction between adjacent interconnects. In particular, the interconnect capacitance has become a far more important component of interconnect delay. Interconnect capacitance arises mainly from two components. Interconnect capacitance has an interconnect-to-substrate component and an interconnect-to-interconnect component. The interconnect-to-interconnect component is primarily a result of plate capacitance and Miller capacitance. The plate capacitance is the result of the plate area and the distance between the sides of adjacent interconnects. The Miller capacitance is related to the simultaneous movement of signals on closely spaced interconnects. Interconnect-to-interconnect capacitance may also be referred to as coupling capacitance.
The interconnect-to-substrate component of interconnect capacitance is well understood. After integrated circuits were reduced in size enough that interconnect capacitance became a limitation, it was the interconnect-to-substrate component that was the dominant factor with relatively short and thick interconnects. The interconnect-to-substrate component is relatively easy to model since it does not depend upon independent variables such as the type of traffic carried on neighboring interconnects. Since interconnects have become thinner and relatively taller, the interconnect-to-substrate capacitance component of interconnect capacitance has diminished and the interconnect-to-interconnect component has become the critical design limitation.
As mentioned above, the interconnect-to-interconnect plate capacitance component is generally related to the geometry of the interconnects and the distance to neighboring interconnects. This makes the plate capacitance component, like the interconnect-to-substrate capacitance, a relatively easy to model component. One of the challenging aspects of the Miller capacitance component of interconnect delay in the design of integrated circuits is that it is dependent upon the direction and the type of signal traveling on neighboring interconnects, the system architecture, and the system timing. Therefore, the Miller capacitance cannot be easily predicted or modeled.
The timing of the entry of a signal on an interconnect is generally a function of the integrated circuit clock and the integrated circuit architecture. The signal entry timing may also be affected by the processing being performed at any functional block. These signal entry timing factors are well understood in the field. Integrated circuit designers, using well known software, base computer models of integrated circuits in part on these well known signal entry timing factors.
Uncertainty and unpredictability in any integrated circuit component leads to over design. The unpredictability of the Miller capacitance has lead to over design. Designers typically assume the worst case scenario in regard to Miller capacitance and increase the distance between interconnects to reduce the worst case effects of Miller capacitance.
In the typical integrated circuit, the direction of signal travel on interconnects is primarily a function of the integrated circuit architecture. The designer typically simply determines two nodes on functional blocks that require connection and runs a line between the two nodes. Although there is no predetermined method for placing interconnects traveling in the same direction next to each other, the typical integrated circuit architecture generally leads to a series of neighboring interconnects having signals traveling in the same direction. Since the Miller capacitance is related to the simultaneous movement of signals on closely spaced interconnects, Miller capacitance plays a large part in interconnect delay of neighboring interconnects having signals traveling in the same direction.
The typical integrated circuit is no longer a single layer device. The proportional affect of interconnect-to-interconnect capacitance compared to interconnect-to-substrate capacitance is even more important when the layering of interconnect layers is considered. To meet the designers' goals, integrated circuits are increasingly becoming layered devices. As upper layers move further away from ground the interconnect-to-interconnect capacitance becomes more much important than interconnect-to-ground capacitance. Because of the interconnect-to-interconnect capacitance, integrated circuit designers typically allow large margins-of-error in designing interconnect layouts. The Miller capacitance is an even greater cause of large margins-of-error in upper layers than in lower layers. Thus interconnect-to-interconnect capacitanc

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