Interupt vectoring for trace exception facility in computer syst

Details Interupt vectoring for trace exception facility in computer syst Interupt vectoring for trace exception facility in computer syst

1996-04-18

1999-10-05

Ellis, Richard L.

395568, 395733, G06F 900

Patent

active

059637374

ABSTRACT:
An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.

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