Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1999-03-02
2002-05-28
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S047000, C710S058000, C713S600000
Reexamination Certificate
active
06397272
ABSTRACT:
BACKGROUND OF THE INVENTION
In a system which controls two or more peripheral devices by a data processor such as a microcomputer, the data processor not only sends a control instruction to each peripheral device but also receives signals from each peripheral device as well, i.e., the exchange of signals between them is not unidirectional but bidirectional. The data processor receives an event signal by an interruption at any time from each peripheral device as well, thereby monitoring conditions of such peripheral devices and making a response to them, if necessary.
An interruption processing circuit is thus provided as an interface to input event signals coming from many peripheral devices to the data processor.
When any event occurs in peripheral devices, an event signal outputted from such devices is inputted to the interruption processing circuit. The event signal is then written on a specified register embedded in the interruption processing circuit. The event signal written on the register is held and stored therein until it is read into the data processor. The data processor, by reading the signal written on each register to be used exclusively for each peripheral device, can recognize in which peripheral device the event has occurred.
However, such conventional interruption processing circuits present the following problems.
The interruption processing circuit itself has no function to spontaneously inform a data processor of the occurrence of an event in a peripheral device. Therefore, the data processor has to send a readout signal to the interruption processing circuit in a predetermined cycle to read out a signal stored in a register embedded in the interruption processing circuit.
For example, if the event signal is active when it is a logical “1” and if the logical “1” signal is stored in the register, the data processor recognizes that an event has occurred in the corresponding peripheral device. If a logical “0” signal is stored in the register, the data processor recognizes that no event has occurred in the corresponding peripheral device.
However, an event usually occurs at any given timing in the peripheral device. Moreover, the data processor, because it cannot predict the occurrence of any event, tries to read any signal stored in the said register in a predetermined cycle.
There is, therefore, a case where the timing of the peripheral device's writing of an event signal on said register may be overlapped with that of the data processor's reading of a signal stored in the register. In such a case, the signal level read by the data processor becomes unstable and the data processor may fail to read the signal in some cases.
Furthermore, after the data processor has read the signal stored in the register, it clears the signal in the register and has a logical “0” signal stored in the register. This is done to prepare for writing of a subsequent event signal. As a result, if a peripheral device writes an event signal on the register at the same time when the data processor reads the signal stored in the register, the event signal written on the register is cleared at the subsequent timing. This means that the peripheral device fails to write the event signal on the register. In either case, it causes the data processor to fail to properly recognize the occurrence of an event in the peripheral device and the whole system to fail to fiction properly accordingly.
SUMMARY OF THE INVENTION
The present invention has been made to resolve such problems as described above. An object of the present invention is to provide an interruption processing circuit wherein a data processor does not fail to read an event signal even if the timing at which an event signal is written on the interruption processing circuit is overlapped with the timing at which a signal stored in the interruption processing circuit is read into the data processor.
Another object of the present invention is to provide an interruption processing circuit wherein a peripheral device does not fail to write an event signal even if the timing at which an event signal is written on the interruption processing circuit is overlapped with the timing at which a signal stored in the interruption processing circuit is read into the data processor.
According to the first aspect of the invention, there is provided an interruption processing circuit for receiving and storing an event signal outputted at the occurrence of an event in a peripheral device and for outputting that event signal to a data processor monitoring conditions of the peripheral device comprising a first storage device which, when the event signal is inputted from the peripheral device thereto, receives the event signal and stores it and which, when a processing start timing signal outputted before the data processor reads the event signal is inputted thereto as a control signal, stores a signal being just received and updates contents already stored in synchronization with the processing start timing signal, and a second storage device which, when the processing start timing signal is inputted thereto as a control signal, receives the signal stored before the first storage device updates contents already stored and stores it in synchronization with this processing start signal, and also continues to output the stored signal to the data processor for a period time enough for the data processor to be able to read the event signal.
In the preferred mode of the invention, wherein an output circuit is provided which is inserted into a path through which an event signal is outputted from the second storage device to the data processor and which allows the event signal outputted from the second storage device to pass therethrough from the time when the processing start timing signal becomes inactive to the time when the information readout signal being continuously outputted while the data processor is reading the event signal becomes inactive.
In another preferred mode of the invention, wherein the first storage device is provided with a first flip-flop which stores a received signal and feeds an output to the second storage device and with a first selector which selects either of a signal received in an input terminal or a signal stored in the first flip-flop and stores it into the first flip-flop; the first selector operating so as to select the signal received at the input terminal if the event signal is inputted to a control terminal and to store it into the first flip-flop and to select the signal inputted to the input terminal if the processing start timing is inputted to the control terminal and to store it into the first flip-flop, and wherein the second storage device is provided with a second flip-flop which stores the signal received from the first storage device and with second selector which selects either of a signal received from the storage device or a signal stored in the second flip-flop and stores it into the second flip-flop, the second selector selecting the signal received from the first storage device before contents stored in the flip-flop is updated if the processing start timing signal is inputted to the control terminal, and contents stored in the second flip-flop being initialized by a clearing signal inputted into the control terminal after the data processor has completed the readout of the event signal.
According to the second aspect of the invention, there is provided an interruption processing circuit for receiving and storing data outputted at the occurrence of an event in a peripheral device and for outputting that data to a data processor monitoring conditions of the peripheral device comprising a first storage device which, when the data is inputted from the peripheral device thereto, receives that data and stores it and which, when a processing start timing signal outputted before the data processor reads the data is inputted thereto as a control signal, stores data being just received and updates contents already stored in synchronization with this processing start timing signal, and a second storage d
Frank Robert J.
Lee Thomas
Mai RiJue
Oki Electric Industry Co. Ltd.
Venable
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